CMPE 315: Principles of VLSI Design

CMPE 315: Principles of VLSI Design
Section 01
Spring 2021

Instructor: Chintan Patel
Office: ITE 322
Office Hours: Mon & Wed, 4:00 PM - 5:30 PM or by appointment

Teaching Assistants:
Vrajesh Mistry :
Dhandeep Challagundla :
Office Hours: TBD

Meeting Time and Location:Tues & Thrs, WEB, 4:00 - 5:15 PM
Lab Discussion: Fri, WEB/ITE375, 1:00 - 2:50 PM
Lab: Fri, WEB/ITE 375 (use according to instructions), 3:00 - 4:00 PM

Check regularly for important class information

 Syllabus posted.

Course Material

 Syllabus: Fall 2020 syllabus

 Lecture 1: Introduction

 Lecture 2: CMOS Basics I

 Lab Submission
  • Completely fill out and include the cover page (doc, html, pdf) with each lab submission.
  • Labs will not be accepted without it.
  • Late submission penalty is 20% lab grade per day late.
  • Weekends will be considered as late days.


 Project Description

 Project Waveforms

 Example test benches and correct outputs

 Project Submission I Details (VHDL code & Report)

 Instructions for running VNC on ITE375 machines

 Instructions for running cadence tools

 DRC rules for AMI 0.6um technology (Available at MOSIS site)

 Cadence Incisive (VHDL) Tutorial

 Cadence IC6 Tutorials

 Cadence IC5 Tutorials (OLD TOOLS, USE IC6 TUTORIALS)

 VHDL Help