Instructor: Chintan Patel
Office: ITE 322
Office Hours: Mon & Wed, 4:00 PM - 5:30 PM or by appointment

Teaching Assistants:
Vrajesh Mistry : vmistry1@umbc.edu
Dhandeep Challagundla : vd58139@umbc.edu
Office Hours: TBD

Meeting Time and Location:Tues & Thrs, WEB, 4:00 - 5:15 PM
Lab Discussion: Fri, WEB/ITE375, 1:00 - 2:50 PM
Lab: Fri, WEB/ITE 375 (use according to instructions), 3:00 - 4:00 PM

Check regularly for important class information

 Syllabus posted.

 Syllabus: Fall 2020 syllabus

 Lecture 1: Introduction

 Lecture 2: CMOS Basics I

 Lab Submission

• Completely fill out and include the cover page (doc, html, pdf) with each lab submission.
• Labs will not be accepted without it.
• Late submission penalty is 20% lab grade per day late.
• Weekends will be considered as late days.

 Project Description

 Project Waveforms

 Example test benches and correct outputs

• Use tar -xvf filename to untar. Read the README.ncsim file in each directory for instructions
• Example Test Bench 1
• Example Test Bench 2

 Project Submission I Details (VHDL code & Report)

 Instructions for running VNC on ITE375 machines

 Instructions for running cadence tools

 DRC rules for AMI 0.6um technology (Available at MOSIS site)

• http://www.mosis.org/Technical/Layermaps/lm-scmos_scn3m.html

 Cadence Incisive (VHDL) Tutorial

• Cadence VHLD Tutorial (NCVHDL)

 Cadence IC6 Tutorials

• Cadence Virtuoso Schematic Editor Tutorial
• Analog Design Environment Simulation Tutorial
• Cadence Virtuoso Layout Editor Tutorial

 Cadence IC5 Tutorials (OLD TOOLS, USE IC6 TUTORIALS)

• Cadence Virtuoso Schematic Editor Tutorial
• Analog Design Environment Simulation Tutorial
• Cadence Virtuoso Layout Editor Tutorial
• Cadence Virtuoso Extraction Tutorial (.avi movie file)
• Cadence SpectreS Simulation Tutorial (.avi movie file)
• Cadence Waveform Browser Tutorial (.avi movie file)
• Cadence VHLDIN Tutorial (Importing structural VHDL)

 VHDL Help

• Intro to VHDL
• A Simple VHDL Example: Inverter
  • Inverter VHDL description : inverter.vhdl
  • Inverter Test File (using input/output files): inverter_test.vhdl
  • Inverter Input File (for use with inverter_test.vhdl): inverter_in.txt
  • Inverter Output File (output from inverter_test.vhdl): inverter_out.txt
  • NCSIM run file (for use with inverter_test.vhdl): inverter_ncsim.run
  • Inverter Test File (output on stdout/screen): inverter_test_stdout.vhdl
  • NCSIM run file (for use with inverter_test_stdout.vhdl): inverter_ncsim_stdout.run
• Structural VHDL Example: 4-bit Ripple Carry Adder
  • Adder VHDL description : adder4.vhdl
  • Adder Test File (using input/output files): adder4_test.vhdl
  • Adder Input File (for use with adder4_test.vhdl): adder4_in.txt
  • Adder Output File (output from adder4_test.vhdl): adder4_out.txt
  • NCSIM run file (for use with adder4_test.vhdl): adder4_ncsim.run
  • To run the stdout version testfile below use the -v93 option with ncvhdl and ncelab
  • Adder Test File (output on stdout/screen): adder4_test_stdout.vhdl
  • NCSIM run file (for use with adder4_test_stdout.vhdl): adder4_ncsim_stdout.run
• Transmission Gate VHDL code
• Negative Edge Triggered D Flip Flop VHDL code
• Positive Level Sensitive Larch VHDL Code
• Useful VHDL information and links: Do not use the cadence VHDL setup information on this site. Use what we discussed in class (as given in the tutorial)