The 80x87 is able to multiply, divide, add, subtract, find the sqrt and calculate transcendental functions and logarithms.
Data types include 16-, 32- and 64-bit signed integers; 18-digit BCD data; and 32-, 64- and 80-bit (extended precision) floating-point numbers.
The directives dw, dd and dq are used for declaring signed integer storage while dd, dq and dt are used for floating-point.
Converting from decimal to floating-point is accomplished:
n
Convert the decimal number into binary.
n Normalize the binary number.
n Calculate the biased exponent.
n Store the number in the floating-point format.
Bias is 0x7F, 0x3FF and 0x3FFF for the 3 floating-point number types.
m
The number 0 is stored as all 0s (except for the sign bit).
m
+/- infinity is stored as logic 1s in the exponent, with a significand of all 0s. Sign bit is used to represent +/- infinity.
m
A NAN (not-a-number) is an invalid floating-point result that has all 1s in the exponent with a significand that is NOT all zeros.
Converting from floating-point to decimal is accomplished:
m Separate the sign-bit, biased exponent, and significand.
m Convert the biased exponent into a true exponent by subtracting the bias.
m Write the number as a normalized binary number.
m Convert it to a de-normalized binary number.
m Convert the de-normalized binary number to decimal.
The 80x87 executes 68 different instructions.
Basic structure of the co-processor.
Coprocessor Status Register
The registers in the coprocessor stack always contain 80-bit extended precision data.
Memory data, of course, can assume other representations. Therefore, conversions occur during transfers.
FSTSW AX (Floating-point STore Status Word).
An instruction that transfers data between the coprocessor and the AX register.
Error conditions can be checked in your program by examining bits of this status word.
You can use the TEST instruction to test bits or the SAHF instruction to transfer the left-most 8 bits to the EFLAGs register.
Coprocessor Status/Control Register
This register selects precision, rounding control and infinity control.
For example, a value of 00 for P and C sets single precision mode.
R and C control rounding, e.g. round down, up or truncate toward 0.
Coprocessor Instruction Set
Data Transfer Instructions:
Loads floating-point data to Stack Top (ST). Stack pointer is then decremented by 1.
Data can be retrieved from memory, or another stack position.
Note that ST is register 0 after initialization.
m
FST (Store Real),
FSTP (Store Real and Pop)
Stores a copy of the top of the stack (and pop for FSTP) into memory or another coprocessor register.
Rounding occurs when the storage operation completes according to the control register.
Exchanges register given as operand with ST.
m
FCMOV (Conditional floating point MOV)
Coprocessor Instruction Set
Integer Data Transfer Instructions:
m
FISTP (Store integer and pop)
Similar to
FLD,
FST and
FSTP except they transfer (and convert) integer.
Stack addressing mode is restricted to use ST (stack top) and ST1.
The source operand is ST while the destination operand is ST1.
After the operation, the source is
popped, leaving the dest. at ST.
Coprocessor Instruction Set
Arithmetic Instructions (cont):
Note that
FSUB subtracts ST from ST1, e.g., ST = ST1 - ST.
Use
FSUBR to reverse the order.
For example, to compute the reciprocal (1/X):
Register addressing mode MUST use ST as one of the operands.
The other operand can be any register, including ST0 which is ST.
Note that the destination can be either ST or STn.
Also, unlike stack addressing, non-popping versions can be used.
Memory addressing mode always uses ST as the destination.
Coprocessor Instruction Set
Arithmetic Instructions (cont):
The following letters are used to additionally qualify the operation:
m P: Perform a register pop after the operation,
FADD and
FADDP.
m R: Reverse mode for subtraction and division.
m I: Indicates that the memory operand is an integer. I appears as the second letter in the instruction, e.g.,
FIADD,
FISUB,
FIMUL,
FIDIV.
Arithmetic Related Instructions:
m
FSQRT: Finds the square root of operand at ST. Leave result there. Check IE bit for an invalid result, e.g., the operand was negative using FSTSW AX, and TEST AX, 1.
m
FSCALE: Adds contents of ST1 (interpreted as an integer) to the
exponent of ST.
m
FPREM1: Performs modulo division of ST by ST1. The resultant remainder is found at ST.
m
FRNDINT: Rounds ST to an integer.
Coprocessor Instruction Set
Arithmetic Related Instructions (cont):
m
FXTRACT: Decomposes ST into an unbiased exponent and a significand. Extracted significand is at ST and unbiased exponent at ST1.
m
FABS: Change sign of ST to positive.
m
FCHS: Invert sign of ST.
These instructions examine ST in relation to another element and return result of the comparison in the status register bits C3-C0.
m
FCOM: Compares ST with an memory or register operand. FCOM by itself compares ST and ST1.
m
FCOMP/
FCOMPP: Compare and pop once or twice.
m
FICOM/
FICOMP: Compare ST with integer memory operand and optionally pop the stack.
m
FTST: Compare ST with 0.0.
m
FXAM: Exam ST and modify CC bits to indicate whether contents are positive, negative, normalized, etc. (See text).
m
FCOMI/
FUCOMI: Combines FCOM, FNSTSW AX, and SAHF.
Coprocessor Instruction Set
Transcendental Operations: (See text for semantics).
m
FYL2XP1: Compute Ylog
2(X + 1)
Constant Returning Operations:
m
FLDZ: Store +0.0 to ST.
m
FLD1: Store +1.0 to ST.
m
FLDL2T: Store log
210 to ST.
m
FLDL2E: Store log
2e to ST.
m
FLDLG2: Store log
102 to ST.
m
FLDLN2: Store log
e2 to ST.
Coprocessor Instruction Set
Coprocessor Control Instructions:
m
FINIT/
FNINIT: Reset coprocessor with or without waiting afterwards.
m
FWAIT: Stops microprocessor until coprocessor has finished an operation. Should be used before the microprocessor accesses memory data that are affected by the coprocessor.
Instruction reference is given in text along with examples.
