Basic Architecture Basic components Basic Architecture Bus Architecture: The Pentium bus architecture is not this simple. We will elaborate on this later. Basic Bus Architecture Bus Architecture:- Three buses: m Address: If I/O, a value between 0000H and FFFFH is issued. If memory, it depends on the architecture: 20-bits (8086/8088) 24-bits (80286/80386SX) 25-bits (80386SL/SLC/EX) 32-bits (80386DX/80486/Pentium) 36-bits (Pentium Pro/II/III) m Data: 8-bits (8088) 16-bits (8086/80286/80386SX/SL/SLC/EX) 32-bits (80386DX/80486/Pentium) 64-bits (Pentium/Pro/II/III) m Control: Most systems have at least 4 control bus connections (active low). MRDC (Memory ReaD Control), MWRC, IORC (I/O Read Control), IOWC. Basic Bus Architecture Bus Standards: m ISA (Industry Standard Architecture): 8 MHz 8-bit (8086/8088) 16-bit (80286-Pentium) m EISA: 8 MHz 32-bit (older 386 and 486 machines). m PCI (Peripheral Component Interconnect): 33 MHz 32-bit or 64-bit (Pentiums) New: PCI Express and PCI-X 533 MTS m VESA (Video Electronic Standards Association): Runs at processor speed. 32-bit or 64-bit (Pentiums) Only disk and video. Competes with the PCI but is not popular. Basic Bus Architecture Bus Standards: m USB (Universal Serial Bus): 1.5 Mbps,12 Mbps and now 480 Mbps. Newest systems. Serial connection to microprocessor. For keyboards, the mouse, modems and sound cards. To reduce system cost through fewer wires. m AGP (Advanced Graphics Port): 66MHz Newest systems. Fast parallel connection: Across 64-bits for 533MB/sec. For video cards. To accommodate the new DVD (Digital Versatile Disk) players. Latest AGP 3.0 with peak bandwidth of 2.1GB/s. Basic Memory Architecture Bank layout Basic Memory Architecture Bank layout Basic Memory Architecture Bank layout Basic I/O Architecture Interrupt Vectors (DOS PC) I/O Space It is important to notice that these I/O addresses are NOT memory-mapped addresses on the 80x86 machines. Special instructions (IN/OUT) are used to communicate to the I/O devices.
