Systems Design and Programming
Barry B. Brey, 'The Intel Microprocessors, 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium and Pentium Pro Processor, Pentium II, Pentium III and Pentium 4, Architecture, Programming and Interfacing' Sixth Edition, Prentice Hall (2003).
Muhammad Ali Mazidi and Janice Gillispie Mazidi, 'The 80x86 IBM PC and Compatible Computers (Volumes I&II), Assembly Language, Design, and Interfacing', Third Edition, Prentice Hall (2000).
Bob Neveln, 'Linux Assembly Language Programming', Prentice Hall PTR.
http://www.cs.umbc.edu/~cpatel2
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Intel 80x86 assembly language.
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Architecture of the Intel microprocessors.
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Hardware configuration and control of:
Common microprocessor support chips, e.g. Interrupt controller.
Popular I/O devices, e.g. UART, sound card.
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Experience with the C programming language.
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Some familiarity with Operating Systems, such as Windows.
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Experience with the Linux operating system.
n Assembly Language Programming
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2 microseconds clock cycle time; 500,000 instructions/sec.
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8-bit microprocessor - upgraded version of the 8080.
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1.3 microseconds clock cycle time; 769,230 instructions/sec.
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Intel sold 100 million copies of this 8-bit microprocessor.
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4- or 6-byte instruction cache.
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Other improvements included more registers and additional instructions.
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16-bit microprocessor very similar in instruction set to the 8086.
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4.0 MIPS (250 ns/8MHz).
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Memory management unit added.
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Variations: DX, EX, SL, SLC (cache) and SX.
80386SX: 16MB through a 16-bit data bus and 24 bit address bus.
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32-bit microprocessor, 32-bit data bus and 32-bit address bus.
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20-50MHz. Later at 66 and 100MHz
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Incorporated an 80386-like microprocessor, 80387-like floating point coprocessor and an 8K byte cache on one package.
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About half of the instructions executed in 1 clock instead of 2 on the 386.
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Variations: SX, DX2, DX4.
DX2: Double clocked version:
66MHz clock cycle time with memory transfers at 33MHz.
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32-bit microprocessor, 64-bit data bus and 32-bit address bus.
1-and-1/2 100MHz version.
Double clocked 120 and 133MHz versions.
Fastest version is the 233MHz (3-and-1/2 clocked version).
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16KB L1 cache (split instruction/data: 8KB each).
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Memory transfers at 66MHz (instead of 33MHz).
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Dual integer processors.
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32-bit microprocessor, 64-bit data bus and 36-bit address bus.
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16KB L1 cache (split instruction/data: 8KB each).
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Memory transfers at 66MHz.
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32-bit microprocessor, 64-bit data bus and 36-bit address bus.
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32KB split instruction/data L1 caches (16KB each).
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Module integrated 512KB L2 cache (133MHz).
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Memory transfers at 66MHz to 100MHz (1998).
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32-bit microprocessor, 64-bit data bus and 36-bit address bus.
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32KB split instruction/data L1 caches (16KB each).
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On-chip 256KB L2 cache (at-speed).
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Memory transfers 100MHz to 133MHz.
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Dual Independent Bus (simultaneous L2 and system memory access).
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1.4 to 1.9GHz and the latest at 3.20 GHz and 3.46GHz (Hyper-Threading)!
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1MB/512KB/256KB L2 cache.
n 800 MHz (about 6.4GB/s)/533 MHz (4.3 GB/s)/ 400MHz (3.2 GB/s) system bus.
n 1066 MHz front side bus just available.
n Specialized for streaming video, game and DVD applications (144 new SIMD 128-bit instructions).
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0.13um, more than 55 million transistors, 60nm transistors.
n Newer ones are in 90nm transistors, more than 125 million possible.
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