CMSC 411 — Spring 2018

Final Exam Review Guide

CMSC 411 Final Exam Study Guide

The final exam will be cummulative, but will be weighted towards topics from the second half of the course. So you should review the midterm study guide (available here), also.

The exam will consist of True/False, short answers, one or two longer answers, and some design diagrams. It will be open-book and open-notes.

Final Exam Topic Outline:

• Single Cycle Control Path
  • Modelling CPU operation as logical register transfers
  • 5 Steps:
    
    • ISA requirements
    • Datapath component selection
    • Datapath assembly
    • Analysis of instructions for datapath control
    • Assembly of control logic
• Multi-cycle Control Path
  • Motivation for multi-cycle control path:
    • Faster clock + reduced CPI
  • Needs intermediate storage (registers) to hold temporary results
  • Modelled using FSMs
  • Micro-programmed implementation:
    • Motivation
    • Vertical vs. horizontal microcode
    • Pros and cons to microprogramming
  • Exceptions
    
    • Interrupts vs. traps
    • Support for handling exceptions
• Pipelining
  • Motivation for pipelining
  • Pipelining as extension of multi-cycle design
  • How pipelining improves performance
  • Data stationary for storing stage results
  • Degree of pipelining parallelism
  • Typical stages
    • Instruction fetch
    • Reg fetch, instr decode
    • Execute
    • Memory load/store
    • Reg. write-back
  • Pipeline Hazards
    • Structural hazard
    • Data hazard
    • Control hazard
  • Implementing a pipeline
  • Resolving structural hazards
    • Analyze circuit, add more components
    • Inserting stalls
  • Resolving data hazards
    
    • Data forwarding
    • Inserting bubbles
    • Inserting stalls
  • Resolving control hazards
    
    • Stalls (not good if excessive)
    • Delayed branching
    • Branch prediction: static and dynamic
• Instruction-level Parallelism
  • Multiple issue
    • Static vs. dynamic multiple issue
• Memory Hierarchy
  • DRAM vs. Cache
  • Cache consistency
    • Write-through vs. write-back
  • Cache architectures
    • Direct-mapped
    • Fully associative
    • N-way set associative
  • Block replacement strategies
  • Multi-level cache
• Virtual Memory
  • Virtual addresses vs. physical addresses
  • Page tables
    • Page table entries: valid, read-only bits
    • Multi-level page tables
  • Translation Lookaside Buffers (TLBs)
• I/O Systems
  • Throughput vs. response time
  • Redundant Array of Inexpensive Disks (RAID)
  • I/O control architectures:
    • Programmed I/O vs. Memory-mapped I/O
    • Polled vs. interrupt-driven vs. DMA
• Buses
  • What is a bus?
  • Synchronous vs. Asynchronous
  • Bus arbitration techniques
  • Increasing bandwidth