The Workings of an active low input / output Priority
Encoder, the 74LS148
This sequence of simulations, taken from the Tina© Software suite, illustrates how priority is given
to the inputs depending on the particular input that is active in a priority encoder.
Note that in order for outputs to correspond with the state of the inputs, the input enable pin has to
be asserted: In active low logic, assertion is achieved by bringing the level on the pin to logic 0.
INPUT STATE A Disabled device. EI is not asserted.
INPUT STATE B Device enabled ( EI = 0). Output EO is asserted indicating that if there may
be other processes elsewhere that should be checked for priority. GS is not asserted => none of the
inputs {0..7} have priority, because none of them are asserted.
INPUT STATE C Device enabled (EI = 0) as before. Output EO is not asserted indicating that
there may not be priorities set beyond this IC. GS asserted => an input should be checked to see if
it has priority. Port 7 is asserted. {A2..A0} reads as a 7 in active low output terms.
What happens if we have both SW8 and a lower level switch such as SW5 asserted? See input state
D which follows.
should be checked to see if it has priority. Port 7 is asserted. We have brought SW5 into a logic 0
state which sets port 4 to logic 0 as well this time. But {A2..A0} reads as a 7 in active low output
terms. Clearly port 4 does NOT have priority over port 7. This also applies to the other ports
below 7 in ranking which is ALL the other ports.
INPUT STATE E Device enabled (EI = 0); Output EO is asserted, GS asserted => an input
should be checked to see if it has priority. Two switches are asserted this time.
Which ports are asserted? (Cross out the ones that are NOT)
7 6 5 4 3 2 1 0
Which of the asserted ports has priority now? Port X has priority where X = ______.
Write down what A2, A1, A0 will be (asserted logic 0s): {A2, A1, A0} = { }.
DETERMINATION OF STATE E - Device enabled (EI = 0); Output EO is asserted, GS
asserted => an input should be checked to see if it has priority. Three switches are asserted this
time, resulting in ports 4, 1 and 0 being asserted. Port 4 has priority over the remaining two
asserted ports. Port X=4 has priority where X=(4)BASE10 = (100)BASE2. {A2, A1, A0} = {L, H, H}.
TRUTH TABLE FOR 74LS148 Priority Encoder --- Complete this
Port
Inputs |
Enable Input |
Port Assigned Priority |
Output Enable |
Group Select |
Port Selected |
|||||||||
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
EI |
A2 |
A1 |
A0 |
EO |
GS |
|
x |
x |
x |
x |
x |
x |
x |
x |
H |
H |
H |
H |
H |
H |
none |
H |
H |
H |
H |
H |
H |
H |
H |
L |
H |
H |
H |
L |
H |
remote |
x |
x |
x |
x |
x |
x |
x |
L |
L |
L |
L |
L |
H |
L |
7 |
|
|
|
|
|
|
|
|
L |
|
|
|
H |
L |
6 |
|
|
|
|
|
|
|
|
L |
|
|
|
H |
L |
5 |
x |
x |
x |
x |
L |
H |
H |
H |
L |
L |
H |
H |
H |
L |
4 |
|
|
|
|
|
|
|
|
L |
|
|
|
H |
L |
3 |
|
|
|
|
|
|
|
|
L |
|
|
|
H |
L |
2 |
x |
L |
H |
H |
H |
H |
H |
H |
L |
H |
H |
L |
H |
L |
1 |
L |
H |
H |
H |
H |
H |
H |
H |
L |
H |
H |
H |
H |
L |
0 |