UMBC CMSC 211 Fall 1999

CSEE | 211 | 211 F'99 | lectures | news | help


The Serial Ports - COM X

Parallel transfers are done with all bits being transmitted at the same time, with each bit being transferred down a separate wire in the cable. Serial transfers are done by sending one bit at a time down the same wire.

Sending or receiving one byte of data through the serial channel actuall involves transferring the following sequence of bits:

This transfer takes place at a speed (measured in bauds).

A special chip, the Intel UART8250 (Universal Asynchronous Receiver Transmitter) was designed to support serial data transfers. Access to this chip is thorough the I/O ports.

MS-DOS support two basic communications ports - COM1 and COM2. Their base addresses are stored in the BIOS data area at 0040:0000h (COM1) and 0040:0002h (COM2). The ports used by COM1 and COM2 are not fixed, but 3F8h and 2F8h are common, but so is the reverse. Alway get the port numbers from the BIOS data area. Many different devices can be connected via the serial ports.

The 8250 chip is programmed by 10 one-byte registers, available through the corresponding I/O ports. Some registers are write-only, some are read only and the remainder can be both.

The Asynchronous Adapter Registers
Port Mode value DLAB Meaning
3F8h OUT 0 Transmitter holding register
3F8h IN 0 Receiver holding register
3F8h OUT 1 Divisor latch (low byte)
3F9h OUT 1 Divisor latch (high byte)
3F9h OUT 0 Interrupt enable register
3FAh IN   Interrupt identification register
3FBh OUT   Line control register
3FCh OUT   Modem control register
3FDh IN   Line status register
3FEh IN   Modem status register

This range covers only 7 addresses, you can increase the number of registers actually available to 10 by setting the 7th bit of the line control register (3FBh). This bit is called DLAB - Divisor Latch Access Bit).

Levels of controlling the serial ports

The three ways of controlling ports are: The MS-DOS service provides function 40h (Write File with Handle) of interrupt 21h. This method treats the communications port as a standard file named AUX with a logical number (descriptor) equal to 3. (This is only for COM1.) it is set to 2400 baud with no parity control, one stop bit and 8 bits per symbol.

You can use the BIOS service through interrupt 14h. These functions allow you to initialize the port, set parameters for transferring data such as number of stop bits, the type of parity control and the speed of transfer. however, it will only allow you to set the speed to 9600 baud.

Low-level programming lets you use all the UART 8250 chip facilities, including working with the transfer speed to 115K and over, but requires that the hardware interrupt related to communications ports be processed by your program.

Peripheral Interface - PPI

The PPI was originally based on the 8255A chip, and is used for controlling the keyboard, the internal sound generator, and for getting information about the system configuration.

The 8255A chip is controlled by the ports that are attached to it.

The Programmable Peripheral Interface
Denotation Address Type Purpose
Port A 60h R/W Keyboard input
Port B 61h R/W Configuratin info, speaker and keyboard control
Port C 62h R Get system information
  63h R Mode control for ports A-C
  h4h R Keyboard status (AT or PS/2)

Port B of PPI - The Port 61h
Bit Meaning
0 Timer 2 gate (speaker)
1 Timer 2 data
2 Must be 0
3 1 = read high switches; 0 = read low swithces
4 0 = enable RAM parity checking; 1 = disable
5 0 = enable I/O channel check
6 0 = hold keyboard clock low
7 0 = enable keyboard; 1 = disable keyboard

Contents of PPI Port A (Bit 7 of Port B is set)
Bit Contents
0 0 - no floppy drives
1 Not used
2-3 The number of memory banks on the system board
4-5 Display mode
  11 = monochrome
  10 - color 80x25
  01 - color 40x25
6-7 PC: The number of floppy disk drives

The Contents of Port C
Bit Meaning
0 Values of DIP switches as in Equipment List
1 "
2 "
3 "
4 Must be 0
5 If set - Time channel 2 out
6 if set - I/O channel check
7 if set RAM parity check error occurred

The Interrupt Controller - Intel 8259

The 8259 is also known as the PIC (Programmable Interrupt Controller) and it ensures that hardware interrupts are processed according to their priorities. The interrupt singal is generated by the hardware and sent to the microprocessor to inform it that the hardware state has changed and certain operations need to be performed.

In order to handle multiple interrupts occurring at the same time, there are 8 or 16 interrupt levels (using one or two 8259's). We know them as IRQ0 - IRQ7 and IRQ8 - IRQ15. The smaller the number, the higher the priority is for that interrupt. The highest priority IRQ0 is for the system timer. IRQ1 is for the keyboard. There is an interrupt vector in the BIOS for each IRQ. You can disable some or all of the interrupts. You disable all of them with the CLI (Clear Interrupt) and enable all of them with STI (Set Interrupt). NOTE: IRQ2 (I/O channel) can not can not be disabled and is called a non-maskable interrupt.

There is an Interrupt Mask Register (IMR) that allows you to disable only certain interrupts. The least significant bit is IRQ0 and if it is set to 1, the interrupt is disabled. The first 8 interrupts are controlled through port 21h and the second 8 are controlled through port 0A1h.

The Hardware Interrupts
Level VectorEnable MaskDisable MaskMeaning
IRQ0 08h XXXX XXX0 XXXX XXX1 Timer
IRQ1 09h XXXX XX0X XXXX XX1X Keyboard
IRQ2 0Ah XXXX X0XX XXXX X1XX I/O channel
IRQ3 0Bh XXXX 0XXX XXXX 1XXX COM2 (AT), COM1 (XT)
IRQ4 0Ch XXX0 XXXX XXX1 XXXX COM1 (AT), COM2 (XT)
IRQ5 0Dh XX0X XXXX XX1X XXXX HDD (LPT2 for AT)
IRQ6 0Eh X0XX XXXX X1XX XXXX FDD controller
IRQ7 0fh 0XXX XXXX 1XXX XXXX LPT1
IRQ8 70h XXXX XXX0 XXXX XXX1 Real-time Clock
IRQ9 71h XXXX XX0X XXXX XX1X Translated into IRQ2
IRQ10 72h XXXX X0XX XXXX X1XX Reserved
IRQ11 73h XXXX 0XXX XXXX 1XXX Reserved
IRQ12 74h XXX0 XXXX XXX1 XXXX Reserved
IRQ13 75h XX0X XXXX XX1X XXXX Math co-processor
IRQ14 76h X0XX XXXX X1XX XXXX HDD controller
IRQ15 77h 0XXX XXXX 1XXX XXXX reserved

The Programmable Timer

The timer has three channels and operate at 1.193Mhz under control of the 8284A generator. The channels are available through ports 40h, 41h, and 42. The command register is available through port 43h.
The Programmable Timer Command Register
Bit Meaning
0 0 - binary data, 1 - BCD
1-3 Number of mode used (000-101)
4-5 Operation Type
  00 - send the value of counter
  01 - read/write high byte
  10 - read/write low/byte
  11 - read/write both high and low bytes
6-7 Number of channel to be programmed

Channel 0 is used by teh system clock to calculate the time of day. It is programmed for 18.2 pulses per second (called ticks) and stored in the BIOS data area at 0040h:006Ch. Every pulse initiates a timer interrupt 8h (IRQ0). Don't mess with this one!

Channel 1 is responsible for refreshing RAM and counts the pulses during disk operations, so that it can reset the timer counter upon completion of an operation. This is also not a good one to mess with.

Channel 2 (port 42h) is connected to the computer's speaker and issues square wave pulses used to make sounds. You can change the sound frequency with this channel.The 8255 chip, (PPI) is also involved in generating sound and that bits 0 and 1 of port 61h also control the speaker.

Example program

;***************************************************************
;  Program Sound ( Chapter 10 )
;
;  The program for outputting a sound of prescribed tone
;
;  Author: A.I.Sopin   Voronezh, Russia   1990 --- 1992
;  ------
;
;  Call from Assembler programs:
;
;       Call SOUND
;
;  Parameters passed through the registers:
;
;  Frequency    - DI register (from   21  to  65535  hertz)
;
;  Duration      -BX register (in hundredth of second)
;
;  Registers  AX, CX, DX, DS, ES, SI  are retained by the program 
;
;
;
;***************************************************************
PUBLIC   SOUND
CODE     SEGMENT
         ASSUME CS:CODE
SOUND    PROC   FAR
         push   ax
         push   cx
         push   dx
         push   ds
         push   es
         push   si
;-----------------------------------------------------------
         in     al,61h            ;  Read current port mode B (8255)
         mov    cl,al             ;  Save current mode
         or     al,3              ;  Switch on speaker and timer
         out    61h,al            ;
         mov    al,0B6h           ;  set for channel  2 (8253)
         out    43h,al            ;  command register  8253
         mov    dx,14h            ;
         mov    ax,4F38h          ;  divisor of frequency
         div    di                ;
         out    42h,al            ;  lower byte of frequency
         mov    al,ah             ;
         out    42h,al            ;  higher byte of frequency
;  Generation of sound delay 
         mov    ax,91             ;  multiplier  -  AX register !
         mul    bx                ;  AX =BX*91 (result in   DX:AX)
         mov    bx,500            ;  divisor, dividend in   DX:AX
         div    bx                ;  result in   AX, remainder in DX 
         mov    bx,ax             ;  save result
         mov    ah,0              ;  read time
         int    1Ah               ;
         add    dx,bx             ;
         mov    bx,dx             ;
Cycle:   int    1Ah               ;
         cmp    dx,bx             ;  Has time gone ?
         jne    Cycle             ;
         in     al,61h            ;  Read mode of port B (8255)
         mov    al,cl             ;  Previous mode 
         and    al,0FCh           ;
         out    61h,al            ;  Restore mode
;-----------------------------------------------------------
;  Restoring registers and exit
Exit:    pop    si                ;
         pop    es                ;
         pop    ds                ;
         pop    dx                ;
         pop    cx                ;
         pop    ax                ;
         RETF                     ; exit from subroutine
SOUND    ENDP
CODE     ENDS
         END

  

CSEE | 211 | 211 F'99 | lectures | news | help