CMSC 611, Fall 1998
Assigned: Tuesday, November 17, 1998
Due Tuesday, November 24, 1998 (in class)
- Problem 5.1 from the text.
- You just purchased a new computer, and want to know whether there's enough extra main memory bandwidth to add a new peripheral. Your measurements of the computer have found the following information:
- Hit rate for the D-cache is 98%, and the I-cache has a 99.5% hit rate.
- Block size for the D-cache is 1 word, and for the I-cache is 2 words.
- The processor runs at 250 MHz and has a native CPI of 1.2 without memory accesses.
- 15% of all instructions are loads, and 5% are stores.
- The bus can only support single word operations (i.e., two memory accesses require two complete bus cycles and memory latencies).
- The memory can handle 10 million references per second (i.e., memory cycle time is 100 ns).
- What is the memory utilization if the cache is write-through?
- What is the memory utilization if the cache is write-back? Assume that 40% of the data blocks are dirty.
- Problem 5.5 from the text.
- You want to build a system that can run at 250 native MIPS (including memory stalls). Youre given a 500 MHz CPU with a CPI of 0.4 excluding memory stalls. The CPU has a split onboard L1 cache, with 8 byte data blocks and 32 byte instruction blocks. The instruction cache has a hit rate of 99%, while the data cache has a hit rate of 95%. 40% of the misses in the writeback data cache require the replacement of a dirty block. In this system, 20% of the instructions are loads and 10% are stores.
This system can have 1, 2, or 4 banks of main memory, each 64 bits wide. There is a single bus connecting the banks to the caches; while the banks can all fetch or store data in parallel, only one bank can transfer data on a given bus cycle. The bus has separate addresses and data lines. Costs for system components of various speeds are as follows:
Memory access time
Cost (per bank)
- If cost were no object, how fast could the system be made to run?
- How fast is the cheapest memory system that will meet your design goal of 250 native MIPS?
- Problem 5.8 from the text.
- Problem 5.14 (part a only) from the text.
- Problem 5.21 from the text.
17 Nov 1998