top Project Status (09/02/2013 - 14:17:11)
Project File: counter.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc5vlx110t-1ff1136
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 35 69,120 1%  
    Number used as Flip Flops 35      
Number of Slice LUTs 61 69,120 1%  
    Number used as logic 59 69,120 1%  
        Number using O6 output only 2      
        Number using O5 output only 30      
        Number using O5 and O6 27      
    Number used as exclusive route-thru 2      
Number of route-thrus 32      
    Number using O6 output only 32      
Number of occupied Slices 17 17,280 1%  
Number of LUT Flip Flop pairs used 61      
    Number with an unused Flip Flop 26 61 42%  
    Number with an unused LUT 0 61 0%  
    Number of fully used LUT-FF pairs 35 61 57%  
    Number of unique control sets 2      
    Number of slice register sites lost
        to control set restrictions
1 69,120 1%  
Number of bonded IOBs 10 640 1%  
    Number of LOCed IOBs 10 10 100%  
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
Average Fanout of Non-Clock Nets 2.84      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Sep 2 14:14:09 2013001 Info (0 new)
Translation ReportCurrentMon Sep 2 14:14:19 2013000
Map ReportCurrentMon Sep 2 14:14:58 2013006 Infos (0 new)
Place and Route ReportCurrentMon Sep 2 14:15:49 2013000
Power Report     
Post-PAR Static Timing ReportCurrentMon Sep 2 14:16:11 2013002 Infos (0 new)
Bitgen ReportCurrentMon Sep 2 14:17:05 2013001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun Jan 9 12:40:24 2011
WebTalk ReportCurrentMon Sep 2 14:17:05 2013
WebTalk Log FileCurrentMon Sep 2 14:17:11 2013

Date Generated: 09/02/2013 - 14:17:11