Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/tbench |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2011-01-09T13:19:34 |
PROP_intWbtProjectID=C15FB99411B645E38A94F55A6882294B |
PROP_intWbtProjectIteration=5 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.tbench |
PROP_AutoTop=true |
PROP_DevFamily=Virtex5 |
PROP_DevDevice=xc5vlx110t |
PROP_DevFamilyPMName=virtex5 |
PROP_DevPackage=ff1136 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-1 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=2 |