The goal of the semester project is to design and simulate a pipelined RISC CPU. Major components will be the pipelined ALU data path, the instruction decoder, hazard detection and associated forwarding/stall and cache memory controller.
The project is to be submitted in three incremental parts:
PART1: Handle lw, sw, add, sub, ai, shl, shr and nop with no hazards.
(nop's will be inserted to prevent hazards.)
See opcodes below for detailed instruction formats and definitions.
You should use pipe2.e as a start for coding your circiut.
For grading reasons, keep the signal names *_s2, *_s3, *_s4 that
are pipeline registers and the component/memory names
inst_mem.mr, greg.mr, dmem.mr .
Run your circut with part1.run to be sure it works!
Submit all components and your main circuit as one plain text
file by EMail. No makefiles or run files or output is to be
submitted. Partial credit will be given based on number of
instructions simulated correctly. pipe2.e only simulates lw.
PART2: Handle hazards. Detect hazards, prevent wrong results by data
forwarding where possible and then stall when necessary. Handle
jump and beq instructions as well as all in part1.
Note: jump and beq are followed by a delayed branch slot that
contains an instruction that is always executed. jump can not
cause a stall. beq does not get data forwarding, thus can stall,
and stall, and stall.
Data forwarding paths must cover at least those in Fig 6.51, p499.
Implement your circuit assuming that software has correctly
filled the delayed branch slot and implement the branch in
the ID pipeline phase (e.g. Fig 6.51, Page 499)
For grading reasons, keep the signal names *_s2, *_s3, *_s4 that
are pipeline registers and the component/memory names
inst_mem.mr, greg.mr, dmem.mr and pc for program counter.
Run your circut with part2.run and part2b.run to be sure it works!
Download files part2.chk and part2b.chk to check answers:
ecomp your_part2.e -o part2.net
esim < part2.run > part2.out
diff part2.out part2.chk
Then repeat for part2b which tests branching (beq and jump)
Submit all components and your main circuit as one plain text
file by EMail. No makefiles or run files or output is to be
submitted. Partial credit will be given based on number of
data forwards, jump, beq, and hazard stalls handled correctly.
Do not implement data forwarding into stage 1 (ID) for the beq
instruction.
This is possible, but it will mess up the automatic checking.
Your circuit will not be tested with jump or branch addresses greater
than 15 bits.
PART3: Put a cache in the instruction memory (read only) and a cache
in the data memory (read/write)
Put the caches inside the inst_mem and dmem components.
Use the existing mr as the main memory.
Make a miss on the instruction cache cause a four cycle stall.
Make a miss on the data cache cause a eight cycle stall.
Fig 7.10, page 557 is a possible read only cache for inst_mem.
(75% credit if everything works to this point.)
Do a write through cache for the data memory.
(It must work to the point that results in main memory are
correct at the end of the run, partial credit for
partial functionality)
For grading reasons, keep the signal names *_s2, *_s3, *_s4 that
are pipeline registers and the component/memory names
inst_mem.mr, greg.mr, dmem.mr .
Run your circut with part3.run and check against part3.chk
to be sure it works!
Submit all components and your main circuit as one plain text
file by EMail. No makefiles or run files or output is to be
submitted. Partial credit will be given based on number of
instructions simulated correctly, number of hazards handled
correctly and proper operation of Icache and Dcache.
Last updated 4/30/98