CS411 Downloadable Source and Executables

  These files should be downloaded, only some may be viewed.
  In Netscape this may be  RIGHT CLICK  rather than left click.

  You may also be able to copy files from PC, Linux or SGI's
  "gl machines" from  /afs/umbc.edu/users/s/q/squire/pub/download

Contents by groups of files

Example VHDL files

• Sample VHDL files with annotation/explaination
• t_table.vhdl compute truth tables for std_logic
• add_g.vhdl generic std_logic adder entity
• cntr_g.vhdl generic std_logic counter entity
• mux_g.vhdl generic std_logic multiplexor entity
• reg_g.vhdl generic std_logic register entity
• test_g.vhdl generic std_logic test for above generic entities
• test_g.out generic std_logic test output
• add32b.vhdl 32 bit adder, one behavioral model
• add32_test.vhdl test bench for 32 bit adder
• add32_test.run Cadence ncvhdl -v93 run file
• add32_test.out output of simulating add32_test on Cadence
• sqrt8.vhdl integer square root of 8-bit numbers
• sqrt8.gif schematic of integer square root of 8-bit numbers
• sqrtsm.gif schematic of Sm Subtractor Multiplexor component
• sqrt8.out output of integer square root of 8-bit numbers
• sqrt8m.vhdl improved integer square root of 8-bit numbers
• sqrt8m.gif schematic of improved integer square root of 8-bit numbers
• sqrt8m.out output of improved integer square root of 8-bit numbers
• sqrt32.vhdl integer square root of 32-bit numbers

Esim related files for CS 411 pre 2001

• .esimrc for your login directory
• ecomp.linux ecomp executable for Linux on PC
• esim.linux esim executable for Linux on PC
• ecomp executable for irix.gl.umbc.edu
• esim executable for irix.gl.umbc.edu
• esim - Tutorial for use with next two documents
• ecomp - The esim language
• esim - Simulator control instructions

Esim sample files

• Makefile for your CS411 homework directory
• testadd4.e sample test case for your CS411 homework directory
• testadd4.run sample esim input for your CS411 homework directory
• greg.e general register sample and test driver for esim
• greg.run general register simulator control file
• greg.out general register simulation output
• greg.make general register Makefile
• mux4_8.e multiplexer sample test driver with counter for esim
• mux4_8.run multiplexer sample simulator control file
• mux4_8.out multiplexer sample simulation output
• mux4_8.make multiplexer Makefile
• add4c.e four bit fast carry adder for homework 4
• tadd32c.e test 32 bit fast carry adder for homework 4
• tadd32c.run .run file for homework 4
• tadd32c.chk check file for homework 4
• mul_ser.e for Homework 6 (old)
• mul_ser.run for Homework 6 (old)
• mul_ser.out information for homework 6 (old)
• div_ser.e for Homework 6 (old)
• div_ser.run for Homework 6 (old)
• div_ser.out information for homework 6 (old)

Performance Related Files

• time_test.c checks time() from time.h
• time_cpu.c checks clock() from time.h
• matmul.c for Homework 3 (old)
• matmul2.c for Homework 3
• reglist.txt - register naming and usage conventions

CS 411 project starter files VHDL

• add4.vhdl rename to add32.vhdl and add required HW4 logic
• add32_test.vhdl for testing add32.vhdl from HW4
• add32_test.out for checking that HW4 is correct
• mul_ser.vhdl serial multiplier for use in HW6
• div_ser.vhdl serial divider for use in HW6
• mul_out.vhdl serial multiplier test output
• div_out.vhdl serial divider test output
• cs411_opcodes.txt the subset of MIPS opcodes for CMSC411 project
• pipe1.vhdl fetch an instruction and move it along pipeline
• pipe1.chk output of pipe1.vhdl move instruction along pipeline
• pipe2.vhdl five stage pipeline with memories
• pipe2.chk output of pipe2.vhdl load word, "lw" working
• bshift.vhdl a barrel shifter for sll, srl and sra 32 bit shifts
• test_bshift.vhdl test of bshift.vhdl (complete file)
• test_bshift.out results of simulating test_bshift.vhdl
• part1_start.vhdl CS411 project starter code, five stage pipeline
• part1_start.chk output of part1_start.vhdl load word, "lw" working
• part1.chk Your project part1 should be like this
• part2a.chk Your project part2a should be like this
• part2b.chk Your project part2b should be like this
• part3a.chk Your project part3a should be like this
• part3b.chk Your project part3b should be like this

CS 411 project starter files pre 2001

• pipe1.e fetch an instruction and move it along pipeline
• pipe1.run - for - esim < pipe1.run > pipe1.out
• pipe1.out - shows the clock number and instructions in the pipeline
• pipe1.gif - circuit diagram
• pipe2.e run some load instructions and some noop instructions
• pipe2.run - for - esim < pipe2.run > pipe2.out
• pipe2.out - shows registers in the pipeline and memories
• pipe2.gif - circuit diagram - Page 467, Fig 6.25 simplified
• opcodes.txt - opcodes for PROJECT
• shift.e test circuit for barrel shifter
• shift.run - for - esim < shift.run > shift.out
• bshift.e - barrel shifter component for project
• add32.e - 32 bit adder
• part1.run - for project - esim < part1.run > part1.out
• part1.out - CHECK RESULTS - esim < part1.run > part1.out
• part2.run - for project - esim < part2.run > part2.out
• part2.chk - CHECK RESULTS - diff part2.out part2.chk
• part2b.run - for project - esim < part2b.run > part2b.out
• part2b.chk - CHECK RESULTS - diff part2b.out part2b.chk
• part3a.run - for project - esim < part3a.run > part3a.out
• part3a.chk - CHECK RESULTS - diff part3a.out part3a.chk
• part3b.run - for project - esim < part3b.run > part3b.out
• part3b.chk - CHECK RESULTS - diff part3b.out part3b.chk

Files that may be of historical interest

 many of these are TTL circuits from the '70s 

• D flip flop built with nand gates, tested as a counter
• D flip flop counter esim run file, counter output
• D flip flop counter output, just before clock fall
• D flip flop counter esim run file, full trace
• D flip flop counter output, full trace
• D flip flop - six nand gate model schematic
• JK flip flop built with nand gates, tested as a counter
• JK flip flop counter esim run file, counter output
• JK flip flop counter output, just before clock fall
• JK flip flop counter esim run file, full trace
• JK flip flop counter output, full trace
• JK flip flop - nine nand gate model schematic
• JK flip flop ripple counter schematic

CS 451 files

• Turing machine simulator, C++ source code
• Nondeterministic Turing machine simulator, C++ source code
• Deterministic Finite Automata simulator, C++ source code
• Nondeterministic Finite Automata simulator, C++ source code
• CYK Parser (need 6 files), C++ source code cykp.cpp
• ckyp.h
• cyk_eliminate.cpp
• cyk_chomsky.cpp
• cyk_greibach.cpp
• cyk_parse.cpp
• CYK algorithm code (not runnable, see above)
• CYK algorithm output
• More information on simulators, input and output

CS 109 files, C++

• Directory of C++ files used in CMSC 109

CS 291A files, C++

• Directory of C++ files used in CMSC 291A

Numerics Related Files

• Suite of ISO Numerics and extensions in Ada95
• Suite of ISO Numerics and extensions in Ada83
• LAPACK information

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Last updated 1/23/02