Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 2.2, Build#6.
Copyright(C) Symphony EDA 1997-2003. All rights reserved.

Usage: vhdle [options] entity[(architecture-name)]
Available options are:
    -h             -- Print this help
    -s             -- Enables silent mode
    -work libname  -- Specifies the work library (default is 'work')
    -strict        -- Forces strict VHDL compliance (can slow down simulation)
    -ini filename  -- Explicity specify the INI file name to use
    -nostderr      -- Output all messages to stdout (batch only)
    -t time[unit]  -- Simulate for the amount of time specified (batch only)
    -do cmdfile    -- Read command file for batch mode (batch only)
    -list listfile -- Use file name as list file name (Default simili.lst) (batch only)
    -iterlimit nnn -- Set the iteration limit where nnn is a number (default = 500)
    -p             -- Supresses progress information (speeds up simulation) (batch only)
    -gName=value   -- Override generic value for the top level entity
    -GName=value   -- Override generic value for ALL entities in design
    -sdf[min|typ|max] [InstancePath=]SdfFileName
    -stdin file    -- Use specified file-name as TEXTIO input file
    -stdout file   -- Use specified file-name as TEXTIO output file
    -noaccel name  -- Disable acceleration for given name
	-- 'name' can be one of 1164, std_logic_arith, numeric_bit,
	   numeric_std, vital or ALL
	-- You can specify -noaccel option multiple times
    -nowarn name   -- Disable warnings out of specified accelerated package
	-- 'name' can be one of numeric_bit, numeric_std, std_logic_arith or ALL
    -nowarnmsg name-- Disable specific compier/simulator warning messages
	-- 'name' can be one of the warning identifiers (such as CSVHE0053) or ALL
    -nocycleopt    -- Disable delta cycle optimization
    -noifopt       -- Disable if/then/else optimization
    -breakon sev   -- Stop simulation for errors of given severity
	-- 'sev' can be one of NOTE, WARNING, ERROR, FAILURE. Default is FAILURE
    -coverage file -- Specify code-coverage database file name
    -coverageini file -- Specify code-coverage exception file

Design-unit Specification Examples:
    vhdle myentity
	-- Simulates using myentity's last compiled architecture
    vhdle myentity(myarch)
	-- Simulates the architecture 'myarch' of the entity 'myentity'
    vhdle myconfiguration
	-- Simulates the entity/architecure specified by 'myconfiguration'
    vhdle -work mylib myentity
	-- Simulates the last compiled arch. of 'myentity' from library 'mylib'
    vhdle -work mylib myentity(myarch)
	-- Simulates the arch. 'myarch' of 'myentity' from library 'mylib'

Vital/Sdf Examples:
    vhdle -sdf    /u0/u1=mysdf.sdf myentity
	-- Applies SDF file mysdf.sdf (typical) to the instance /u0/u1
    vhdle -sdfmin /u0=musdf1.sdf -sdfmax /u1=mysdf2.sdf myentity
	-- Multiple SDF file annotation example
    vhdle -sdftyp /=mysdf.sdf myentity
    vhdle -sdftyp mysdf.sdf myentity
	-- Two examples annotating an SDF file to the very top level
  Note: '/' represents a hierarchy separator and instances names are case-sensitive
  Note: Versions of SDF supporeted: 2.1
  Note: Versions of Vital supported: Vital95, Vital 3.0, IEEE 1076.4-Oct-95

Maximum simulation time Example:
    vhdle -t 100ns myentity
	-- Simulate for 100 nanoseconds and stop
    vhdle -t ms myentity
	-- Simulate for 1 millisecond and stop
    vhdle myentity
	-- Automatically stop simulation when all activity has stopped
  Note: If -t is not specified, simulation will end when activity ends
  Note: White space between the Unit-name and the number not allowed