Cases for stall hazards (taking into account data forwarding)
  based on cs411 schematic. This is NOT VHDL, just definitions.

  Note: ( OP stands for opcode, bits (31 downto 26)
          lw stands for load word opcode "100011"
          addi stands for add immediate opcode "000111" etc.
          rr_op stands for OP = "000000" )

  lw  $a, ...
  op  $b, $a, $a  where op is rr_op, beq, sw

      stall_lw is EX_OP=lw and EX_RD/=0 and
                  (ID_reg1=EX_RD or ID_reg2=EX_RD)
                  and ID_OP/=lw and ID_OP /=addi and ID_OP/=j

      (note: the above handles the special cases where
       sw needs both registers. sll, srl, cmpl have a zero in unused register)


  lw  $a, ...
  lw  $b,addr($a)  or addi $b,addr($a)

      stall_lwlw is EX_OP=lw and EX_RD/=0 and
                    (ID_OP=lw or ID_OP=addi) and
                    ID_reg1=EX_RD


  lw  $a ...
  beq $a,$a, ...

      stall_mem is ID_OP=beq and MEM_RD/=0 and MEM_OP=lw and
                   (ID_reg1=MEM_RD or ID_reg2=MEM_RD)


  op  $a, ...   where op is rr_op and addi
  beq $a,$a, ...  

      stall_beq is ID_OP=beq and EX_RD/=0 and
                   (ID_reg1=EX_RD or ID_reg2=EX_RD)


  ID_RD is 0 for ID_OP= beq, j, sw, stall (nop automatic zero)
           thus EX_RD, MEM_RD, WB_RD = 0 for these instructions

  rr_op is add, sub, cmpl, sll, srl

  stall is  stall_lw or stall_lwlw or stall_mem or stall_beq



  stall clock is:

     for falling edge registers    clk and not stall

     for raising edge registers    clk or stall  (our circuit)