Debugging VHDL (or almost any computer input)

  1) Expect errors. Nobody's perfect.


  2) Automate to make it easy to re-run, e.g. Makefile

     In Makefile, keep adding more tests

     all: tadd32.out  pmul8_test.out part1.out
          # these are the final result files

          # <tab> not spaces, precede ncvhdl, ncelab, ncsim

     tadd32.out: add32.vhdl tadd32.vhdl tadd32.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 tadd32.vhdl
	ncelab -v93 tadd32:circuits
	ncsim -batch -logfile tadd32.out -input tadd32.run tadd32
                                   # blank line ends commands

     pmul8_test.out: pmul8.vhdl pmul8_test.vhdl pmul8_test.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 mul_div_ser.vhdl
	ncelab -v93 mul_div_ser:schematic
	ncsim  -batch -logfile mul_div_ser.out \ 
               -input mul_div_ser.run  mul_div_ser

    part1.out: part1.vhdl add32.vhdl bshift.vhdl part1.chk \ 
                                     part1.abs part1.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bshift.vhdl
	ncvhdl -v93 part1.vhdl
	ncelab -v93 part1:schematic
	ncsim  -batch -logfile part1.out -input part1.run part1
        diff -w part1.run part1.chk


  3) tcsh
     source vhdl_cshrc
     gmake    # results come to screen
              # "don't know how to make xxx.yyy" file missing or typo
              # much output flying by on screen, use:
     gmake |& more   # hit space for next page, enter for next line
     gmake >& part1.prt  # results, including error go to a file
                         # use editor to read file, you can search


  4) FIX THE FIRST ERROR !!!!
     Yes, you can fix other errors also, but one error can cause
     a cascading effect and produce many errors.

     Don't panic when there was only one error, you fixed that,
     then the next run you get 37 errors. The compiler has stages,
     it stops on a stage if there is an error. Fixing that error
     lets the compiler move to the next stage and check for other
     types of errors. Go to step 3)


  5) Don't give up. Don't make wild guesses. Do experiment with
     one change at a time. You may actually have to read some
     of the handouts :)


  6) Your circuit compiles and simulates but the output is not
     correct. Solution: add debug print.

     Most circuits in this course have a print process. You can
     easily add printout of more signals. Look for the existing
     code that has 'write' and 'writeline' statements.
     To print out some signal, xxx, after a 'writeline' statement add

           write(my_line, string'("  xxx=")); -- label printout
           hwrite(my_line, xxx);              -- hex for long signals
           write(my_line, string'("  enb="));
           write(my_line, enb);               -- bit for single values
           writeline(output, my_line);        -- outputs line


  7) You have a signal that seems to be wrong and you can not find
     when it gets the wrong value. OK, create a new process to
     print every change and when it occurs.

     prtxxx: process (xxx)
               variable my_line : LINE; -- my_line needs to be defined
             begin
               write(my_line, string'("xxx="));
               write(my_line, xxx);         -- or hwrite for long signals
               write(my_line, ",  string'(at="));
               write(my_line, now);         -- "now" is simulation time
               writeline(output, my_line);  -- outputs line
             end process prtxxx;

     When adding 'write' statements, you may need to add the
     context clause in front of the enclosing design unit. e.g.
        library STD;
        use STD.textio.all; -- defines LINE, writeline, etc.
        library IEEE;
        use IEEE.std_logic_1164.all;
        use IEEE.std_logic_textio.all; -- defines write on std_logic (_vector)


  8) Read your code.
     Every identifier must be declared before it is used.
     Every signal MUST be set exactly once, e.g.
         xxx <= a;
         xxx <= b; -- somewhere else, BAD !

         a0: fadd port map(a(0), b(0), cin , sum(0), c(0));
         a1: fadd port map(a(1), b(1), c(0), sum(1), c(0));
                                                     ####    BAD !

    Signals must match in type and size. An error having 
    "shape mismatch" means incompatible size. You can not put
    one bit into a 32 bit signal nor 32 bits into a one bit signal.
    "...type... error" Are you putting an integer into a std_logic?
    You can not put an identifier of type std_logic into
    std_logic_vector.  a(31 downto 28) is of type std_logic_vector,
    a(31) is of type std_logic.