// projl4.v  Verilog 4 bits times 4 bits made with  madd4 modules
// run  verilog -q -l proj4_v.out proj4.v
`timescale 1ns/1ns
  
module madd(c, b, m, a, sum, cout); // from schematic
  input  c;     // c input
  input  b;     // b input
  input  a;     // a input multiplicand
  input  m;     // m input multiplier
  output sum;   // sum bit output
  output cout;  // carry bit output
  assign sum = (~c&~b&(a&m))|(~c&b&~(a&m))|(c&~b&~(a&m))|(c&b&(a&m));
  assign cout = (c&b)|(c&(a&m))|(b&(a&m));
endmodule // madd

module madd4(a, b, m, sum, cout);
  input [3:0] a;    // a multiplicand
  input [3:0] b;    // sum from previous stage
  input       m;    // multiplier bit
  output [3:0] sum; // stage sum
  output       cout; // stage cout
  wire         zer;
  wire   [3:0] c;
  
  assign zer = 0;
 
  // students project to put 2 more  madd in here
  //      c,    b,    m, a,    sum,    cout
  madd a0(zer,  b[0], m, a[0], sum[0], c[0]);
  madd a1(c[0], b[1], m, a[1], sum[1], c[1]);
   
endmodule // madd4

module proj4;  // test bench
  // signals used in test bench (the interconnections)
  
  reg   [3:0] a; // multiplicand
  reg   [3:0] b; // multiplier
  wire  [7:0] p; // product
  integer     i;
  wire [3:0] zer;
  wire [3:0] sum0;
  wire [3:0] b1;
  wire       cout0;
  // ??? more wires
   
  assign zer = 4'b0000;
 
  // instantiate 4  madd4 with signals
  //       a  b    m     sum   c
  madd4 a0(a, zer, b[0], sum0, cout0);
  assign p[0]  = sum0[0];
  assign b1[0] = sum0[1];
  assign b1[1] = sum0[2];
  assign b1[2] = sum0[3];
  assign b1[3] = cout0;

  // students project to put 3 more madd4 and wiring and reg  here  
  // OK to add  'assign' or other statements (sos on diagram is b1 here)
  madd4 a1(a, b1, b[1], sum1, cout1);
  // ???

  // put in rest 0f p[] ???
   
  initial
    begin  // test cases 

      for(i=0; i<8; i=i+1)
	begin
          a = i;
	  b = ~a;
          #10 $display("a= %b, b=%b, p=%b", a, b, p);
	end
    end
endmodule // proj4