// pipe1.e   fetch instruction and pass through stages (Just a sample)
//           needs add32 component

// component: inst_mem has instruction memory, pc increment and fetch
//  pc is address, inst is instruction read from pc
//  pc gets 4 added to it on falling clk, 4 bytes is one instruction

define inst_mem(pc[32], inst[32], clk)
  memory mr[1024]; // will hold up to 32, 32 bit instructions
  signal four[32] <= #h00000004;
  signal a_in[32];
  signal a_out[32];
  signal cin <= #b0;
  signal cout;
circuits
  mr read inst from pc[6:0].#b000 when #b1; // always available

  // all of this stuff is a sloppy way to increment the pc
  pc_incr use add32(four, a_in, cin, a_out, cout);
  a_in <= pc after 1ns;
  pc <= a_out on falling clk;
  
end circuits;
end inst_mem;


// clock generator and enable controlled counter component

define cntr5(clk, enb, cntr[5]) // 5 bit counter
circuits
  clk <= ~clk after 100ns;
  cntr[0] <= ~cntr[0] when enb else cntr[0] on falling clk after 1ns;
  cntr[1] <= ~cntr[1] on falling cntr[0] after 1ns;
  cntr[2] <= ~cntr[2] on falling cntr[1] after 1ns;
  cntr[3] <= ~cntr[3] on falling cntr[2] after 1ns;
  cntr[4] <= ~cntr[4] on falling cntr[3] after 1ns;
end circuits;
end cntr5;

// IF STAGE SIGNALS - instruction fetch and program counter

signal pc[32] <= #h00000000; // program counter
signal inst[32];             // instruction from memory at program counter

// ID STAGE SIGNALS - instruction decode and register read (write)

signal ir_s1[32]; // Instruction register, pipeline stage 1

// EX STAGE SIGNALS - execute

signal ir_s2[32]; // Instruction register, pipeline stage 2

// MEM STAGE SIGNALS - data memory read and write

signal ir_s3[32]; // Instruction register, pipeline stage 3

// WB STAGE SUGNALS - write back mux

signal ir_s4[32]; // Instruction register, pipeline stage 4

// SYSTEM SIGNALS

signal clk <= #b0; // main system clock
signal cntr[5] <= #b00000;   // just used for output labeling here
signal enb <= #b1;


circuits

// IF STAGE CIRCUITS

  inst_fetch use inst_mem(pc, inst, clk); // inst is the output

// ID STAGE CIRCUITS

  ir_s1 <= inst  on falling clk;   // move instruction through pipeline

// EX STAGE CIRCUITS

  ir_s2 <= ir_s1 on falling clk;   // move instruction through pipeline

// MEM STAGE CIRCUITS

  ir_s3 <= ir_s2 on falling clk;   // move instruction through pipeline

// WB STAGE CIRCUITS

  ir_s4 <= ir_s3 on falling clk;   // move instruction through pipeline

// SYSTEM CIRCUITS

  clock use cntr5(clk, enb, cntr);   // clk and cntr are output

end circuits;