-- pg4.vhdl    entity and architecture
--             Carry-Lookahead unit p246 of textbook
--             pg4 is driven by four add4pg entities 

library IEEE;
use IEEE.std_logic_1164.all;
entity pg4 is 
  port(p0   : in  std_logic;
       p1   : in  std_logic;
       p2   : in  std_logic; 
       p3   : in  std_logic;
       g0   : in  std_logic;
       g1   : in  std_logic;
       g2   : in  std_logic; 
       g3   : in  std_logic;
       cin  : in  std_logic;
       c1   : out std_logic;
       c2   : out std_logic;
       c3   : out std_logic;
       c4   : out std_logic);
end entity pg4 ;

architecture circuits of pg4 is
begin  -- circuits of pg4
  c1   <= g0 or (p0 and cin) after 2 ps;
  c2   <= g1 or (p1 and g0) or (p1 and p0 and cin) after 2 ps;
  c3   <= g2 or (p2 and g1) or (p2 and p1 and g0) or
          (p2 and p1 and p0 and cin) after 2 ps;
  c4   <= g3 or
          (p3 and g2) or
          (p3 and p2 and g1) or
          (p3 and p2 and p1 and g0) or
          (p3 and p2 and p1 and p0 and cin) after 2 ps;
end architecture circuits;  -- of pg4

-- UNCOMMENT LINES BELOW and fill in your HW4

--library IEEE;
--use IEEE.std_logic_1164.all;
--entity add32 is                         -- in file add32pg4.vhdl
--  port(a    : in  std_logic_vector(31 downto 0);
--       b    : in  std_logic_vector(31 downto 0);
--       cin  : in  std_logic; 
--       sum  : out std_logic_vector(31 downto 0);
--       cout : out std_logic);
--end entity add32;

--architecture circuits of add32 is

-- YOUR HOMEWORK 4 GOES HERE

--end architecture circuits;  -- of add32