// mux4_8  four eight bit inputs controlled by CTL to eight bit OUT
define mux4_8(A[8], B[8], C[8], D[8], CTL[2], OUT[8])
circuits
  OUT<= with CTL 
     select
       #b00: A;
       #b01: B;
       #b10: C;
       #b11: D;
       otherwise: A; // can't happen here but syntax requires it
     end select after 1ns;
end circuits;
end mux4_8;

// test circuit that is not part of mux4_8
// note  clk  is a clock with default 10ns width, 100MHz
// note  ctr  is a two bit counter that counts  00, 01, 10, 11, 00, 01 etc
// note the counter is clocked into the control to minimize events

signal a[8] <= #h03;
signal b[8] <= #h0C;
signal c[8] <= #h30;
signal d[8] <= #hC0;
signal ctl[2] <= #b00;
signal out[8];
signal clk <= #b1;     // part of test driver
signal ctr[2] <= #b00; // part of test driver
circuits
  my_mux use mux4_8(a, b, c, d, ctl, out); // component under test
  clk <= ~clk;                                              // test driver
  ctr[0] <= ~ctr[0] on falling clk after 1ns;               // test driver
  ctr[1] <= ~ctr[1] on falling ctr[0] after 1ns;            // test driver
  ctl <= ctr on rising clk after 1ns;               // don't track ripples
end circuits;