// mul_ser.e  multiplier implemented as serial adds (one 32 bit adder)
// needs a 32 bit adder called  add32, else fix to use another adder
// for positive operands, use Booth multiplier for two's complement

// a clock generator and 5 bit counter component
// the user must initialize the cntr to #b00000 and clk to #b1
define cntr5(clk, cntr[5]) // 5 bit counter
circuits
  clk <= ~clk after 15ns;
  cntr[0] <= ~cntr[0] on falling clk     after 1ns;
  cntr[1] <= ~cntr[1] on falling cntr[0] after 1ns;
  cntr[2] <= ~cntr[2] on falling cntr[1] after 1ns;
  cntr[3] <= ~cntr[3] on falling cntr[2] after 1ns;
  cntr[4] <= ~cntr[4] on falling cntr[3] after 1ns;
end circuits;
end cntr5;


// multiplier circuitry, not a component!

signal md[32] <= #h20010007;   // multiplier
signal hi[32] <= #h00000000;   // always starts zero, high order product
signal lo[32] <= #h00000011;   // multiplicand at start, low order product
signal cout;
signal s[32];
signal b[32];                  // output of multiplexer
signal clk <= #b1;             // signals for  cntr5  component, clock
signal cntr[5] <= #b00000;     // value of 5 bit counter
signal enb <= #b1;             // do steps of multiply when  enb is 1
signal mulclk <= #b1;          // gated clock for steps in multiply
circuits 
  counter use cntr5(clk, cntr);
  enb <= #b0 when (cntr==#b11111) else enb on falling clk;
  mulclk <= clk&enb after 1ns; // the multipliers "private" clock

  b  <= md when lo[0] else #h00000000 after 1 ns; // multiplex  md or 0
  adder use add32(hi, b, #b0, s, cout);           // 32 bit adder

  hi <= cout.s[31:1]  on falling mulclk; // note built in shift
  lo <= s[0].lo[31:1] on falling mulclk; // note built in shift
end circuits;