// mul4.v  Verilog 4 bits times 4 bits made with  madd modules
// run  verilog -q -l mul4_v.out mul4.v
`timescale 1ns/1ns
  
module madd(c, b, m, a, sum, cout); // from schematic
  input  c;     // c input
  input  b;     // b input
  input  a;     // a input multiplicand
  input  m;     // m input multiplier
  output sum;   // sum bit output
  output cout;  // carry bit output
  assign sum = (~c&~b&(a&m))|(~c&b&~(a&m))|(c&~b&~(a&m))|(c&b&(a&m));
  assign cout = (c&b)|(c&(a&m))|(b&(a&m));
endmodule // madd

module mul4;  // test bench
  // signals used in test bench (the interconnections)
  
  reg   [3:0] a; // multiplicand
  reg   [3:0] b; // multiplier
  reg 	zer;
  reg 	one; 
  wire  [15:0] sum; // 4*i+j  00=0  10=4  20=8  30=12  33=15 
  wire  [19:0] c;   // intermediate couts 
  wire  [7:0] p;    // product
   
  // instantiate modules with signals
  //          c        b      m     a      sum      c
  madd bit00(zer,     zer,   b[0], a[0],  p[0],    c[0]);
  madd bit01(zer,     zer,   b[0], a[1],  sum[1],  c[1]);
  madd bit02(zer,     zer,   b[0], a[2],  sum[2],  c[2]);
  madd bit03(zer,     zer,   b[0], a[3],  sum[3],  c[3]);

  madd bit10(sum[1],  c[0],  b[1], a[0],  p[1],    c[4]);
  madd bit11(sum[2],  c[1],  b[1], a[1],  sum[5],  c[5]);
  madd bit12(sum[3],  c[2],  b[1], a[2],  sum[6],  c[6]);
  madd bit13(zer,     c[3],  b[1], a[3],  sum[7],  c[7]);

  madd bit20(sum[5],  c[4],  b[2], a[0],  p[2],    c[8]);
  madd bit21(sum[6],  c[5],  b[2], a[1],  sum[9],  c[9]);
  madd bit22(sum[7],  c[6],  b[2], a[2],  sum[10], c[10]);
  madd bit23(zer,     c[7],  b[2], a[3],  sum[11], c[11]);

  madd bit30(sum[9],  c[8],  b[3], a[0],  p[3],    c[12]);
  madd bit31(sum[10], c[9],  b[3], a[1],  sum[13], c[13]);
  madd bit32(sum[11], c[10], b[3], a[2],  sum[14], c[14]);
  madd bit33(zer  ,   c[11], b[3], a[3],  sum[15], c[15]);

  madd bit40(sum[13], c[12], one,  zer,   p[4],    c[16]);
  madd bit41(sum[14], c[13], one,  c[16], p[5],    c[17]);
  madd bit42(sum[15], c[14], one,  c[17], p[6],    c[18]);
  madd bit43(zer  ,   c[15], one,  c[18], p[7],    c[19]);
  
  always
    begin
      $display("mul4.v running");
      zer = 0;
      one = 1;
      a   = 4'b1011;
      b   = 4'b1001; 
      #15 $display("a=%b, b=%b, p=%b", a, b, p);
      $display("c=%b", c);
      $display(" ");
       
      a   = 4'b1111;
      b   = 4'b1111; 
      #15 $display("a=%b, b=%b, p=%b", a, b, p);
      $display("c=%b", c);

      $finish;
    end
endmodule // mul4