// greg  general register set
//  memory is internal, a1 address reads and outputs on out1
//                      a2 address reads and outputs on out2
//                      aw address writes input on wr & clk falling
define greg(a1[5], a2[5], aw[5], input[32], wr, clk, out1[32], out2[32])
memory mr[1024]; // 32 registers of 32 bits each
circuits
  mr read out1 from a1.#b00000 when #b1; // always available
  mr read out2 from a2.#b00000 when #b1;
  mr write input to aw.#b00000 when wr on falling clk;
end circuits;
end greg;


// a little test circuit   not part of  greg  component
signal a1[5] <= #b00010;
signal a2[5] <= #b00011;
signal aw[5] <= #b00010;
signal clk   <= #b1;
signal wr    <= #b1;
signal input[32] <= #hCCCCCCCC;
signal out1[32];
signal out2[32];
circuits
  reg_set use greg(a1, a2, aw, input, wr, clk, out1, out2);
  clk<=~clk after 10ns;
end circuits;