// div_ser.e  division implemented as serial adds (one 32 bit adder)
//            needs component  add32
// non restoring division  (remainder may need correction - in this case
//                          add divisor, because remainder not same sign
//                          as dividend.)

// initialize clk to #b1,  cntr to #b00000
define cntr5(clk, cntr[5]) // 5 bit counter and clock generator
circuits
  clk     <= ~clk after 30ns;
  cntr[0] <= ~cntr[0] on falling clk     after 1ns;
  cntr[1] <= ~cntr[1] on falling cntr[0] after 1ns;
  cntr[2] <= ~cntr[2] on falling cntr[1] after 1ns;
  cntr[3] <= ~cntr[3] on falling cntr[2] after 1ns;
  cntr[4] <= ~cntr[4] on falling cntr[3] after 1ns;
end circuits;
end cntr5;

  //             85 / 7 = 12 with remainder 1 
signal md[32] <= #h00000007; // divisor
signal hi[32] <= #h00000000; // top of dividend (will end up remainder)
signal lo[32] <= #h00000055; // bottom of dividend (will end up quotient)
signal sum[32];
signal cout;
signal a[32]; // shifted dividend
signal b[32]; // md if add, sub_add==0  else  subtract, ~md if sub_add==1
signal quo <= #b0;
signal sub_add <= #b1; // first operation is always subtract (also cin)
signal clk <= #b1;
signal cntr[5] <= #b00000;
signal enb <= #b1;
signal divclk <= #b1;  // only run 32 steps for 32 bit divide

circuits 
  counter use cntr5(clk, cntr);
  enb <= #b0 when (cntr==#b11111) else enb on falling clk; // stop divide
  divclk <= clk&enb after 1ns;

  a  <= hi[30:0].lo[31] after 1ns; // shift
  b  <= ~md when sub_add else md after 1 ns; // subtract or add
  adder use add32(a, b, sub_add, sum, cout);  // note: cin == sub_add
  quo <= ~sum[31] after 1ns; // quotient bit

  hi      <= sum          on falling divclk after 1ns;
  lo      <= lo[30:0].quo on falling divclk after 1ns;
  sub_add <= quo          on falling divclk after 1ns;

end circuits;