// dff_cntr.e   full D flip flop coded as nand gates, tested as counter

//           since nand is not an esim primitive, create a nand gate
define nand(a, b, c, out)
  circuits
    out <= ~(a&b&c) after 1ns;  // not of the and of a, b, c
  end circuits;
end nand;


define dff(d, clk, r, s, q, q_)  //  full D flip flop
                             // d is read on rising clock
                             // clk is typically system clock gated by signal
                             // q is output, q_ is complement output
                             // r is reset, normally high, low to reset (clear)
                             // s is set,   normally high, low to set (preset)
  signal d1, d1_, d2, d2_;   // internal signals
  circuits
    d1  use nand(d1_, s  , d2_, d1 );
    d1_ use nand(d1 , r  , clk, d1_);
    d2  use nand(d2_, d1_, clk, d2 );
    d2_ use nand(d2 , r  , d  , d2_);
    q   use nand(q_ , s  , d1_, q  );
    q_  use nand(q  , r  , d2 , q_ );
  end circuits;
end dff;

// test circuit that makes a four bit counter out of D flip flops
//
signal clk <= #b1;
signal start <= #b1; // used for circuit initialization 
signal reset <= #b1; // reset signal to all D flip flops
signal set   <= #b1; // set   signal to all D flip flops
signal d0, d1, d2, d3;  // D flip flop inputs
signal q0, q1, q2, q3;  // D flip flop outputs
signal q0_, q1_, q2_, q3_; // D flip flop complement outputs (spoken as q0 bar)
// the standard circuit symbol for complement is a bar over the top of a signal

circuits
  clk <= ~clk after 8ns;     // control circuitry
  start <= #b0 after 3ns;    // 1 initially, then always zero
  reset <= ~start after 1ns; // one time reset based on start

  dff0 use dff(d0, clk, reset, set, q0, q0_);
  dff1 use dff(d1, clk, reset, set, q1, q1_);
  dff2 use dff(d2, clk, reset, set, q2, q2_);
  dff3 use dff(d3, clk, reset, set, q3, q3_);

  // circuitry that makes a four bit counter out of D flip flops
  // note the classic structure: state outputs through gates to state inputs
  d0 <= q0_ after 1ns;
  d1 <= (q1&~q0)|(q1_&q0) after 1ns;
  d2 <= (q2&(~q0|~q1))|(q2_&q0&q1) after 1ns;
  d3 <= (q3&(~q0|~q1|~q2))|(q3_&q0&q1&q2) after 1ns;
end circuits;