-- cache memory for hardware solution to part3a
--              this is just the memory part, you implement the cache

library IEEE;
use IEEE.std_logic_1164.all;

entity cache_memory is
  port(index        : in  std_logic_vector (1 downto 0);
       clear        : in  std_logic;
       write_data   : in  std_logic_vector (154 downto 0);
       write_enable : in  std_logic;  -- rising clock and enable
       write_clk    : in  std_logic;  -- required to write
       out_data     : out std_logic_vector (154 downto 0));
end entity cache_memory;

library IEEE;
use IEEE.std_logic_textio.all;
use WORK.util_pkg.all;
use STD.textio.all;

architecture behavior of cache_memory is
  subtype block_type is std_logic_vector(154 downto 0);
  type cache_type is array (0 to 3) of block_type;
  signal cache_ram : cache_type := (others=>(others=>'0'));
begin  -- behavior
  cache_mem: process(index, clear, write_clk)
               variable block_addr : natural;  -- index
             begin
               block_addr := to_integer(index);
               if clear='1' then
                 out_data <= (others=>'0');
               elsif write_enable='1' and write_clk='1' then
                 cache_ram(block_addr) <= write_data;  -- write cache
                 out_data <= write_data;
               else
                 out_data <= cache_ram(block_addr) after 250 ps; -- read cache
               end if;
             end process cache_mem;


  debug:  process -- used to show cache
            variable my_line : LINE;   -- not part of working circuit
          begin
            wait for 9.5 ns;         -- just before rising clock
            for I in 0 to 3 loop
               write(my_line, string'("line="));
               write(my_line, I);
               write(my_line, string'("  V="));
               write(my_line, cache_ram(I)(154));
               write(my_line, string'("  tag="));
               hwrite(my_line, cache_ram(I)(151 downto 128)); -- ignore top bit
               write(my_line, string'("  w0="));
               hwrite(my_line, cache_ram(I)(127 downto 96));
               write(my_line, string'("  w1="));
               hwrite(my_line, cache_ram(I)(95 downto 64));
               write(my_line, string'("  w2="));
               hwrite(my_line, cache_ram(I)(63 downto 32));
               write(my_line, string'("  w3="));
               hwrite(my_line, cache_ram(I)(31 downto 0));
               writeline(output, my_line);
            end loop;
            writeline(output, my_line);  -- blank line
            wait for 0.5 ns;         -- rest of clock
          end process debug;

end architecture behavior;  -- of cache_memory