// 32 bit adder component

// 1 bit stage
define fadd(a, b, cin, s, cout)
circuits
  s <= a ^ b ^ cin after 1ns;
  cout <= (a&b)|(a&cin)|(b&cin) after 1ns;
end circuits;
end fadd;

// 4 bit carry select adder
define add4(a[4], b[4], cin, s[4], cout)
signal c0[4];
signal c1[4];
signal s0[4];
signal s1[4];
circuits
  // the zero carry stages
  s00 use fadd(a[0], b[0], #b0,   s0[0], c0[0]);
  s01 use fadd(a[1], b[1], c0[0], s0[1], c0[1]);
  s02 use fadd(a[2], b[2], c0[1], s0[2], c0[2]);
  s03 use fadd(a[3], b[3], c0[2], s0[3], c0[3]);
  // the one carry stages
  s10 use fadd(a[0], b[0], #b1,   s1[0], c1[0]);
  s11 use fadd(a[1], b[1], c1[0], s1[1], c1[1]);
  s12 use fadd(a[2], b[2], c1[1], s1[2], c1[2]);
  s13 use fadd(a[3], b[3], c1[2], s1[3], c1[3]);
  // select the results
  cout <= c1[3] when cin else c0[3] after 1ns;
  s    <= s1    when cin else s0    after 1ns;
end circuits;
end add4;

define add16(a[16], b[16], cin, s[16], cout)
signal c[3];
circuits
  a0 use add4(a[3:0],   b[3:0],   cin,  s[3:0],   c[0]);
  a1 use add4(a[7:4],   b[7:4],   c[0], s[7:4],   c[1]);
  a2 use add4(a[11:8],  b[11:8],  c[1], s[11:8],  c[2]);
  a3 use add4(a[15:12], b[15:12], c[2], s[15:12], cout);
end circuits;
end add16;

define add32(a[32], b[32], cin, s[32], cout)
signal c[3];
signal s0[16];
signal s1[16];
circuits
  a0 use add16(a[15:0],  b[15:0],  cin, s[15:0],   c[0]);
  a1 use add16(a[31:16], b[31:16], #b0, s0,        c[1]);
  a2 use add16(a[31:16], b[31:16], #b1, s1,        c[2]);
  s[31:16] <= s1 when c[0] else s0 after 1ns;
  cout <= c[2] when c[0] else c[1] after 1ns;
end circuits;
end add32;