# Makefile_ive   iverilog  replacement of Cadence verilog
# iverilog add4.v && a.out > add4_iv.out

all: proj4_iv.out proj5_iv.out

proj4_iv.out: proj4.v
	iverilog proj4.v && a.out > proj4_iv.out
	rm -f a.out
	cat proj4_iv.out

proj5_iv.out: proj5.v
	iverilog proj5.v && a.out > proj5_iv.out
	rm -f a.out
	cat proj5_iv.out