Homework 5

CMSC 411 / Olano, Spring 2012

For this assignment, assume cache sizes given below, and that any relevant page table blocks are in memory.

Level Addressing Block size Capacity Associativity Write policy
TLB   - 256 entries full  
L1 virtual 64 B 32 KB 8-way write-back
L2 physical 64 B 256 KB 8-way write-back
L3 physical 64 B 8 MB 16-way write-back
  1. What are the complete sequence of cache and TLB misses that happen before a page fault?
  2. Why use a virtually addressed L1 and physically addressed L2 and L3?
  3. What data needs to be added to which of these caches/buffers to support multiple processes and shared memory?
  4. Draw a figure similar to figure 5.24 in the book for this system. You can abbreviate any long or wide entries tables by drawing the first and last elements and indicating how many there are.