Jeremy S. Lee is currently a graduate student at the University of Maryland Baltimore County (UMBC) in the Computer Science and Electrical Engineering (CSEE) Department seeking an M.S. degree in Computer Engineering. He received his B.S. in Computer Engineering from UMBC in 2002. He is working as a research assistant in the Computer-Aided Design and Test (CADT) Research Group under the supervision of Dr. Mohammad Tehranipoor.

His current area of research concentrates on the chip testing and security.

The most widely accepted method of chip manufacturing testing has been with scan. While this design for testability (DFT) technique greatly enhances the fault coverage of the chip by increasing the test controllability and observability, it also creates an easily accessible port of attack. The same properties that are beneficial to testing greatly decrease the security of the chip. This is especially harmful if the designer is trying to protect an innovative design or secret key. Modifying scan such that it still provides the same advantages while not retaining the security flaws is a careful balancing act that must become too obtrusive to the original purpose of the chip.