Instructor: Chintan Patel
Office: ITE 322
Office Hours: Mon & Wed, 10:00 - 11:30 AM or by appointment

Teaching Assistants: Ekarat Laohavaleeson (ekarat2@umbc.edu)
Office Hours: Tue & Thrs, 2:30 - 4:00 PM, ITE 201F/ ITE 375 or by appointment

Meeting Time and Location: Mon & Wed, ITE 231, 1:00 - 2:15 PM
Lab Discussion: Fri, ITE 375, 1:00 - 2:50 PM
Lab Section 0101: Fri, ITE 375, 3:00 - 3:50 PM

Check regularly for important class information

 Mar 9: Midterm Exam will be on Wed. Apr 1st in class

 Feb 23: We will be meeting in the lab ITE 375 this Wed. Feb 25th.

 Jan 26: Syllabus posted.

 Syllabus: Spring 2009 syllabus

 Lecture 1: Introduction

 Lecture 2: CMOS Basics I

 Lecture 3: CMOS Basics II

 Lecture 4: IC Technology

 Lecture 5: Circuit and System Representation

 Lecture 6: MOS Details

 Lecture 7: MOS Capacitance and Resistance Model

 Lecture 8: Inverter DC & AC Response

 Lecture 9: CMOS Fabrication I

 Lecture 10: CMOS Fabrication II

End of Midterm Exam Material

 Lecture 11: Circuit Characterization and Performance Estimation

 Lecture 12: Logical Effort

 Lecture 13: Power Dissipation

 Lecture 14: Interconnect and Wire Engineering

 Lecture 15: Design Margin, Reliability and Scaling

 Lecture 16: Combinational Logic Design

 Lecture 17: Combination Logic Design II

 Lecture 18: Sequential Logic Design

End of Course Material

 Lab Submission

• Completely fill out and include the cover page (doc, html, pdf) with each lab submission.
• Labs will not be accepted without it.
• Late submission penalty is 20% lab grade per day late.
• The definition for a late lab is if you don't hand in your lab when you walk into your lab session or class session when it's due, you have a late submission.
• Weekends will be considered as late days.

 Lab Assignment 1 (Due Mon Feb 16): Structural VHDL

• Submit softcopy of the code, via submit. Class name: cmpe315 , Project name: lab1
• Code hardcopy submission: Use Enscript Command
• You can also submit a SINGLE pdf file instead of turning in a hard copy. It should include the lab cover page

 Lab Assignment 2 (Due Wed Feb 25th): Schematics and SpecteS Simulations

 Lab Assignment 3 (Due Fri Mar 6th): Layout, Extraction and Simulations

• Layout Example Slides

 Lab Assignment 4 (Due Fri Mar 13th): D Flip-flop layout and simulations

• Note: This lab is worth 200 points

 Lab Assignment 5 (Due Mon Mar 30th): Import VHDL, layout and LVS

 Project Description

 Project Waveforms

 Project Submission I Details (VHDL code & Schematics)  (Due Apr. 24th)

 Example test benches and correct outputs

• Use tar -xvf filename to untar. Read the README.ncsim file in each directory for instructions
• Example Test Bench 1
• Example Test Bench 2

 Instructions for running cadence tools

 DRC rules for AMI 0.6um technology (Available at MOSIS site)

• http://www.mosis.org/Technical/Layermaps/lm-scmos_scn3m.html

 Cadence Tutorials

• Cadence Virtuoso Schematic Editor Tutorial
• Analog Design Environment Simulation Tutorial
• Cadence Virtuoso Layout Editor Tutorial
• Cadence Virtuoso Extraction Tutorial (.avi movie file)
• Cadence SpectreS Simulation Tutorial (.avi movie file)
• Cadence Waveform Browser Tutorial (.avi movie file)
• Cadence VHLD Tutorial (NCVHDL)
• Cadence VHLDIN Tutorial (Importing structural VHDL)

 VHDL Help

• Intro to VHDL
• A Simple VHDL Example: Inverter
  • Inverter VHDL description : inverter.vhdl
  • Inverter Test File (using input/output files): inverter_test.vhdl
  • Inverter Input File (for use with inverter_test.vhdl): inverter_in.txt
  • Inverter Output File (output from inverter_test.vhdl): inverter_out.txt
  • NCSIM run file (for use with inverter_test.vhdl): inverter_ncsim.run
  • Inverter Test File (output on stdout/screen): inverter_test_stdout.vhdl
  • NCSIM run file (for use with inverter_test_stdout.vhdl): inverter_ncsim_stdout.run
• Structural VHDL Example: 4-bit Ripple Carry Adder
  • Adder VHDL description : adder4.vhdl
  • Adder Test File (using input/output files): adder4_test.vhdl
  • Adder Input File (for use with adder4_test.vhdl): adder4_in.txt
  • Adder Output File (output from adder4_test.vhdl): adder4_out.txt
  • NCSIM run file (for use with adder4_test.vhdl): adder4_ncsim.run
  • To run the stdout version testfile below use the -v93 option with ncvhdl and ncelab
  • Adder Test File (output on stdout/screen): adder4_test_stdout.vhdl
  • NCSIM run file (for use with adder4_test_stdout.vhdl): adder4_ncsim_stdout.run
• Transmission Gate VHDL code
• Negative Edge Triggered D Flip Flop VHDL code
• Useful VHDL information and links: Do not use the cadence VHDL setup information on this site. Use what we discussed in class (as given in the tutorial)