Improvement in high speed DSP applications can be done by integrating computational power with effective memory management. Bandwidth and latency of operation in memory system is rigidly dependent on data accesses. DSP applications such as multimedia require exhaustive streaming at high speed buses. The energy consumption is the key element which will be the focus of research in VLSI and Embedded systems industry. Today a cardinal issue of DSP application is to reduce impact of memory access on execution time while reducing energy consumption of the system. Memory Scheduling is significant in DSP applications to use memory bandwidth effectively. In this paper, we introduce the dynamic memory access scheduling with refresh priority considerations. In addition, a novel bus switching activity monitoring mechanism is implemented to efficaciously reduce the energy consumption of memory operations. H.264/AVC provides higher coding efficiency through added features and functionality, which impose additional computational complexity in encoder and decoder. The features of memory access patterns of H.264 encoder are analyzed. The overhead cycle of page activation has been reduced to improve bus efficiency which also reduces latency of operations. The scheduler and memory controller has been experimented by running a dynamic H.264/AVC application on Xilinx FPGA.
Amey Kulkarni and V.Arunachalam, "FPGA Implementation of Dynamic Energy Efficient Memory Controller for a H.264/AVC Application", International Journal of Computer Application (IJCA), April'2011 Edition
@article{key:article,
author = {A.M. Kulkarni and V. Arunachalam},
title = {FPGA Implementation of Dynamic Energy Efficient Memory Controller for a H.264/AVC Application},
journal = {IJCA Proceedings on International Conference and workshop on Emerging Trends in Technology (ICWET)},
year = {2011},
number = {3},
pages = {44-48},
note = {Published by Foundation of Computer Science}
}