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Verilog Compiler Directives


Compiler directives begin with "`" an accent grave, not an apostrophe
Some of these would be called preprocessor commands in "C"

Compilers may add additional compiler directives. They may not be
portable and may not invoke the same actions. These are from the
Verilog 2001 Standard.

`include file_name   // include source code from another file
`define macro_name macro_code  // substitute macro_code for macro_name
`define macro_name(par1, par2,...) macro_code  // parameterized macro
`undef  macro_name             // undefine a macro

`ifdef  macro_name1    // include source lines1 if macro_name1 is defined
     <source lines1>   // the source lines1
`elsif macro_name2     // any number of elsif clauses, the first defined
     <source lines2>   // macro_name includes the source lines
  `else                // include source lines3 when no prior macro_name defined
     <source lines3>   // the source lines 3
  `endif               // end the construct
  `ifndef macro_name   // like `ifdef except logic is reversed,
                       // true if macro_name is undefined

  `timescale 1ns/1ns   // units/precision for time  e.g. for %t
  `celldefine          // marks beginning of a cell
  `endcelldefine       // marks end of a cell

  `default_nettype net_type  // sets the default net type for implicit
                             // net declarations, net_type is one of:
       // wire, tri, tri0, tri1, triand, trior, trireg, wand, wor, none

  `resetall           // reset all directives to default state,
                      // undefine all macros
  `line number "filename" level // over rides the compilers information
  `unconnected_drive pull0  // set unconnected inputs to 0
  `unconnected_drive pull1  // set unconnected inputs to 1
  `nounconnected_drive      // terminates either of the above directives
  `default_decay_time a_time // sets all undefined trireg net decay times,
                             // a_time is integer, real or infinite
  `default_trireg_strength val // default trireg net strength 0 to 250
  `delay_mode_distributed    // sets distributed delay mode
  `delay_mode_path           // sets path delay mode
  `delay_mode_unit           // sets unit delay mode
  `delay_mode_zero           // sets zero-delay mode

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