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Standard VHDL Packages

VHDL standard packages and types

  The following packages should be installed along with the VHDL
  compiler and simulator.  The packages that you need,
  except for "standard", must be specifically accessed by each of
  your source files with statements such as:

        library IEEE;
        use IEEE.std_logic_1164.all;
        use IEEE.std_logic_textio.all;
        use IEEE.std_logic_arith.all;
        use IEEE.numeric_bit.all;
        use IEEE.numeric_std.all;
        use IEEE.std_logic_signed.all;
        use IEEE.std_logic_unsigned.all;
        use IEEE.math_real.all;
        use IEEE.math_complex.all;

        library STD;
        use STD.textio;

  A version of these packages, declaration and body, are in
  this directory

The package  standard  is predefined in the compiler.
  Types defined include:  bit      bit_vector             typical signals
                          integer  natural  positive      typical variables
                          boolean  string   character     typical variables
                          real     time     delay_length  typical variables
  Click on standard to see the functions defined
  Note: This package must be provided with compiler, do not use this one.


The package  textio  provides user input/output
  Types defined include:     line       text   side    width
  Functions defined include: readline   read
                             writeline  write  endline
  Click on textio to see how to call the functions


The package  std_logic_1164  provides enhanced signal types
  Types defined include:   std_ulogic   std_ulogic_vector
                           std_logic    std_logic_vector
  Click on std_logic_1164 to see available functions


The package  std_logic_textio  provides input/output for 1164 types
  Functions defined include: readline   read
                             writeline  write  endline
  Click on std_logic_textio to see how to call the functions


The package  std_logic_arith  provides numerical computation
  This package name unfortunately seams to have several definitions:

  std_logic_arith_syn.vhd
  defines types  signed  and  unsigned  and
  has arithmetic functions that operate on signal types
  signed  and  unsigned  and  std_logic_vector  and  std_ulogic_vector,
  but adding  A to B of std_logic_vector type, needs  
  unsigned(A) + unsigned(B).
  Click on std_logic_arith_syn to see the functions defined

  std_logic_arith_ex.vhd
  has arithmetic functions that operate on signal types
  std_logic_vector  and  std_ulogic_vector
  Click on std_logic_arith_ex to see the functions defined


The package  numeric_bit  provides numerical computation
  Types defined include:  unsigned  signed   arrays of type bit for signals
  Click on numeric_bit to see the functions defined


The package  numeric_std  provides numerical computation
  Types defined include: unsigned  signed  arrays of type std_logic for signals
  Click on numeric_std to see the functions defined


The package  std_logic_signed  provides signed numerical computation
  on type std_logic_vector

  Click on std_logic_signed to see the functions defined


The package  std_logic_unsigned  provides unsigned numerical computation
  on type std_logic_vector
  Click on std_logic_unsigned to see the functions defined


The package  math_real  provides numerical computation
  on type real

  Click on math_real to see the functions defined
  This declaration and body are in mathpack

The package  math_complex  provides numerical computation
  Types defined include: complex, complex_vector, complex_polar

  Click on math_complex to see the functions defined
  This declaration and body are in mathpack


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