On-chip Scan Enable Generation for Transition Fault Testing

With today\'s design size in millions of gates and working frequency in gigahertz range, 
timing-related defects are high proportion of the total chip defects. Also, very low 
defective parts per million (DPPM) demands has made at-speed test crucial. The transition 
fault model is widely used for detecting delay-induced defects. There are two transition 
fault pattern generation methods; i.e. launch-off-shift (LOS) and launch-off-capture (LOC). 
The LOS method has several advantages over the LOC but imposes strict requirements on 
transition fault testing due to at-speed scan enable signal and tester support. In this 
presentation, we demonstrate two new techniques to generate local scan enable control 
signals with for designs targeted for low cost testers.

A novel scan-based at-speed test method to generate multiple on-chip fast scan enable signals 
is proposed for LOS implementation. The scan enable control information is encapsulated in 
the test data and transferred during the scan operation. A new scan cell, referred to as 
last transition generator (LTG), is inserted in the scan chains	to generate the	fast local 
scan enable signal.

Another new scan-based at-speed test referred to as \"enhanced launch-off-capture\" (ELOC) 
is proposed in which a transition can be launched either from the scan path or the functional 
path. The technique improves the controllability of transition fault testing and it does not 
require the scan enable to change at-speed. The ELOC method provides an intermediate coverage 
between LOS and LOC without any extra effort compared to LOC. Similarly, the scan enable control 
information is encapsulated in the test data and transferred during the scan operation to 
generate the local scan enable signals during the launch and capture cycle. A new scan cell, 
referred to as local scan enable generator (LSEG), is inserted in the scan chains to generate 
the local scan enable signals.

The proposed techniques are robust, practice-oriented in an industrial flow and suitable for 
designs targeted for low cost ATEs.