Logic BIST that combines Random Patterns and Complementary-Weight Weighted Patterns 

The demonstration will show through poster a new efficient 
logic BIST scheme. The BIST implementation combines random
patterns with complementary-weight weighted patterns. BIST
circuitry is implemented outside the core logic. The scheme
is applied on large ISCAS circuits and industrial designs 
with up to 2 million gates. Promising results are achieved 
for industrial designs with high test coverage and very
low hardware overhead. Complete fault coverage are also
obtained for large ISCAS circuits.