A Vector-based Approach for Power Supply Noise Analysis in Delay Test Compaction

To detect small manufacturing defects, at-speed delay testing uses a path delay fault model. 
However, as semiconductor technology is scaled, designs are becoming more and more sensitive 
to power supply noise. Excessive power supply noise has a significant impact on the timing 
performance of deep sub-micron (DSM) designs. For delay tests, random fill of don’t care 
bits can generates excessive circuit activity and noise, causing overkill. Worse, compaction 
alone may generate excessive noise.

We propose a static test vector compaction solution to prevent such overkill.  Our goal is to 
generate compacted vectors with power supply noise up to the mission-mode level on targeted 
paths. It targets either worst-case local voltage noise or worst-case path delay. A novel power 
model for fast vector-based power noise analysis has been developed, which avoids costly power 
network analysis. A linear delay model has been used to calculate path delay under noise. The 
complexity of per-vector supply noise analysis is O(G), for G gates. Experiments have been 
performed on ISCAS benchmarks and an industrial design, with promising results.