// test_dff.v  test  dff.v  with  dff4 level sensitive
//                          and   dff6 edge sensitive
`timescale 1ps/1ps

`include "dff.v"

module test_dff;
  reg d, c, s, r;
  wire q4, q4_, q6, q6_;
  reg clk;

  dff6 d01(d, c, s, r, q6, q6_); // instantiate dff6
  dff4 d02(d, c, q4, q4_);       // instantiate dff4

  initial
    begin
      $display("test_dff testing dff4 and dff6");
      c = 1'b0;
      d = 1'b1;
      s = 1'b1;
      r = 1'b1;
      clk = 1'b0;
      forever #10 clk = ~clk;
    end

  always
    begin
      #10 $display("d=%b, c=%b, s=%b, r=%b", d, c, s, r);
          $display("q4=%b, q4_=%b, q6=%b, q6_=%b", q4, q4_, q6, q6_);
      c = 1'b1;
      #10 $display("d=%b, c=%b, s=%b, r=%b", d, c, s, r);
          $display("q4=%b, q4_=%b, q6=%b, q6_=%b", q4, q4_, q6, q6_);
      c = 1'b0;
      #10 $display("d=%b, c=%b, s=%b, r=%b", d, c, s, r);
          $display("q4=%b, q4_=%b, q6=%b, q6_=%b", q4, q4_, q6, q6_);
      d = 1'b0;
      #2 c = 1'b1; // d must be set before c changes
      #10 $display("d=%b, c=%b, s=%b, r=%b", d, c, s, r);
          $display("q4=%b, q4_=%b, q6=%b, q6_=%b", q4, q4_, q6, q6_);
      c = 1'b0;
      #10 $display("d=%b, c=%b, s=%b, r=%b", d, c, s, r);
          $display("q4=%b, q4_=%b, q6=%b, q6_=%b", q4, q4_, q6, q6_);
      $display("clk=%b at time=%0t ",clk, $time); // just experimenting
      $finish;
    end
endmodule // test_dff