-- pipemul_test.vhdl   test entity pipemul

--signal a[msb];  multiplier   msb=3, 7, 11, 15, ... ,31, 63
--signal b[msb];  multiplicand
--signal p[msb2];  product

-- entity register_32 is  -- for saving a,b 9 clocks, then print with p
--                           comes from compiling pipemul.vhdl

library STD;
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;

entity pipemul_test is
end pipemul_test;

architecture circuits of pipemul_test is
  constant msb  : integer := 31;        -- most significant bit
  constant msb2 : integer := 2*msb+1;   -- double length msb
  constant NS   : integer := 8; -- number of stages in pipemul.vhdl;
  signal cntr   : std_logic_vector(7 downto 0) := X"00";
  signal one    : std_logic_vector(7 downto 0) := X"01";
  signal a      : std_logic_vector(msb downto 0)  := (others => '0');
  signal b      : std_logic_vector(msb downto 0)  := (others => '0');
  signal p      : std_logic_vector(msb2 downto 0) := (others => '0');
  signal clk    : std_logic := '1';        -- clock for pipemul
  signal clear  : std_logic := '1';      -- one time clear
  type aarr is array(0 to NS) of std_logic_vector(31 downto 0);
  signal ain    : aarr;  -- pipeline register input multiplicand a 
  signal aout   : aarr;  -- pipeline register output multiplicand a
  signal bin    : aarr;  -- pipeline register input multiplier b
  signal bout   : aarr;  -- pipeline register output multiplier b

  procedure my_printout(a   : std_logic_vector(msb  downto 0);
                        b   : std_logic_vector(msb  downto 0);
                        p   : std_logic_vector(msb2 downto 0)) is
    variable my_line : line;
  begin
    write(my_line, string'("a="));
    write(my_line, aout(NS));
    write(my_line, string'(", b="));
    write(my_line, bout(NS));
    writeline(output, my_line);
    write(my_line, string'("p="));
    write(my_line, p);
    write(my_line, string'(" at="));
    write(my_line, now);
    writeline(output, my_line);
  end my_printout;
  
begin  -- circuits of pipemul_test
  clear <= '0' after 10 ps;
  clk <= not clk after 500 ps;

  
  mult32: entity WORK.pipemul port map(clk, a, b, p); -- parallel circuit


  -- registers for saving a and b until p is computed
  greg: for j in 0 to NS generate
    aregj: entity WORK.register_32 port map(clk, clear, ain(j),  aout(j));
    bregj: entity WORK.register_32 port map(clk, clear, bin(j),  bout(j));
  end generate greg;
  ain(0)  <= a;                     -- changes when a or b changes
  bin(0)  <= b;                     -- put on aout, bout, pout, tcout  at clk

  -- pass along multiplicand and multiplier
  mpy: for j in 0 to NS-1 generate
    ain(j+1) <= aout(j); -- wiring
    bin(j+1) <= bout(j); -- wiring
  end generate mpy;
  

  driver: process(clk)  -- serial code, create test values of a and b
            variable my_line : LINE;
          begin  -- process driver
            if clk='1' then
              a( 3 downto  0) <= cntr(3 downto 0);
              a( 7 downto  4) <= cntr(3 downto 0);
              a(11 downto  8) <= cntr(3 downto 0);
              a(15 downto 12) <= cntr(3 downto 0);
              a(19 downto 16) <= cntr(3 downto 0);
              a(23 downto 20) <= cntr(3 downto 0);
              a(27 downto 24) <= cntr(3 downto 0);
              a(msb downto msb-3) <= cntr(3 downto 0); -- as many as needed
              b( 3 downto  0) <= cntr(7 downto 4);
              b( 7 downto  4) <= cntr(7 downto 4);
              b(11 downto  8) <= cntr(7 downto 4);
              b(15 downto 12) <= cntr(7 downto 4);
              b(19 downto 16) <= cntr(7 downto 4);
              b(23 downto 20) <= cntr(7 downto 4);
              b(27 downto 24) <= cntr(7 downto 4);
              b(msb downto msb-3) <= cntr(7 downto 4); -- as many as needed
              cntr <= unsigned(cntr) + unsigned(one);
            end if;
          end process driver;

  prtabp: process  -- print a,b,p just before clock
            variable my_line : LINE;
          begin  -- process driver
            wait for 950 ps;
            my_printout(a, b, p);  -- write output
            wait for 50 ps;
          end process prtabp;
            
end architecture circuits; -- of pipemul_test