ncsim: 15.20-s035: (c) Copyright 1995-2017 Cadence Design Systems, Inc. TOOL: ncsim 15.20-s035: Started on Aug 19, 2020 at 21:06:25 EDT ncsim -input part2b.run -batch -logfile part2b.out -messages -cdslib /afs/umbc.edu/users/s/q/squire/home/cs411/vhdl2/cds.lib -hdlvar /afs/umbc.edu/users/s/q/squire/home/cs411/vhdl2/hdl.var part2b Loading snapshot vhdl.part2b:schematic .................... Done ncsim> run 290 ns ---PC--- --inst-- loadmem process input .abs file 00000000 8C0F0074 lw $15,w2($0) 00000004 8C100078 lw $16,w3($0) 00000008 00108844 sll $17,$16,1 -- $16 forwarded after stall 0000000C 02319020 add $18,$17,$17 -- $17 forwarded on both 00000010 76320004 beq $17,$18,lab1 -- $18 forwarded after stall, no branch 00000014 8C010070 lw $1,w1($0) 00000018 08000009 j lab1 0000001C 8C020070 lw $2,w1($0) -- branch slot, always 00000020 8C0A0084 lw $10,w6($0) -- not executed 00000024 AC010074 lab1: sw $1,w2($0) 00000028 AC02007C sw $2,w4($0) 0000002C 74410002 beq $2,$1,lab2 -- no forward, does branch 00000030 8C080074 lw $8,w2($0) -- always execute 00000034 8C090084 lw $9,w6($0) -- not executed 00000038 8C050080 lab2: lw $5,w5($0) 0000003C 74500003 beq $2,$16,lab4 -- no forward, no branch 00000040 8C060084 lw $6,w6($0) 00000044 00A6200F or $4,$5,$6 -- $6 forwarded after stall 00000048 30070070 addi $7,w1($0) 0000004C ACE60000 lab4: sw $6,0($7) 00000050 AC070080 sw $7,w5($0) 00000054 00000000 nop 00000058 00000000 nop 0000005C 00000000 nop 00000060 00000000 nop 00000064 00000000 nop 00000068 00000000 nop 0000006C 00000000 nop 00000070 11111111 w1: word 0x11111111 00000074 22222222 w2: word 0x22222222 00000078 33333333 w3: word 0x33333333 0000007C 44444444 w4: word 0x44444444 00000080 55555555 w5: word 0x55555555 00000084 66666666 w6: word 0x66666666 loadmem ends. memory loaded clock 0 inst=8C0F0074 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 1 inst=8C100078 PC =00000004 PCnext=00000008 ID stage IR=8C0F0074 rd=01111 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 2 inst=00108844 PC =00000008 PCnext=0000000C ID stage IR=8C100078 rd=10000 EX stage IR=8C0F0074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=01111 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 3 inst=02319020 PC =0000000C PCnext=00000010 ID stage IR=00108844 rd=00000 EX stage IR=8C100078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=10000 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C0F0074 addr =00000074 data =00000000 read =22222222 rd=01111 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 4 inst=02319020 PC =0000000C PCnext=00000010 ID stage IR=00108844 write=22222222 into =0000000F rd=10001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =FFFF8844 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C100078 addr =00000078 data =00000000 read =33333333 rd=10000 WB stage IR=8C0F0074 read =22222222 pass =00000074 result=22222222 rd=01111 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 5 inst=76320004 PC =00000010 PCnext=00000014 ID stage IR=02319020 write=33333333 into =00000010 rd=10010 EX stage IR=00108844 EX_A =00000000 EX_B =00000000 EX_C =FFFF8844 rd=10001 EX stage EX_aluB=33333333 EX_res=66666666 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C100078 read =33333333 pass =00000078 result=33333333 rd=10000 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 6 inst=8C010070 PC =00000014 PCnext=00000018 ID stage IR=76320004 rd=00000 EX stage IR=02319020 EX_A =00000000 EX_B =00000000 EX_C =FFFF9020 rd=10010 EX stage EX_aluB=66666666 EX_res=CCCCCCCC MEM stage IR=00108844 addr =66666666 data =33333333 rd=10001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 7 inst=8C010070 PC =00000014 PCnext=00000018 ID stage IR=76320004 write=66666666 into =00000011 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000004 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=02319020 addr =CCCCCCCC data =66666666 rd=10010 WB stage IR=00108844 read =00000000 pass =66666666 result=66666666 rd=10001 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 8 inst=08000009 PC =00000018 PCnext=0000001C ID stage IR=8C010070 write=CCCCCCCC into =00000012 rd=00001 EX stage IR=76320004 EX_A =66666666 EX_B =00000000 EX_C =00000004 rd=00000 EX stage EX_aluB=00000004 EX_res=6666666A MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=02319020 read =00000000 pass =CCCCCCCC result=CCCCCCCC rd=10010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 9 inst=8C020070 PC =0000001C PCnext=00000024 ID stage IR=08000009 rd=00000 EX stage IR=8C010070 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00001 EX stage EX_aluB=00000070 EX_res=00000070 MEM stage IR=76320004 addr =6666666A data =CCCCCCCC rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 10 inst=AC010074 PC =00000024 PCnext=00000028 ID stage IR=8C020070 rd=00010 EX stage IR=08000009 EX_A =00000000 EX_B =00000000 EX_C =00000009 rd=00000 EX stage EX_aluB=00000009 EX_res=00000009 MEM stage IR=8C010070 addr =00000070 data =00000000 read =11111111 rd=00001 WB stage IR=76320004 read =00000000 pass =6666666A result=6666666A rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 11 inst=AC02007C PC =00000028 PCnext=0000002C ID stage IR=AC010074 write=11111111 into =00000001 rd=00000 EX stage IR=8C020070 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00010 EX stage EX_aluB=00000070 EX_res=00000070 MEM stage IR=08000009 addr =00000009 data =00000000 rd=00000 WB stage IR=8C010070 read =11111111 pass =00000070 result=11111111 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 12 inst=74410002 PC =0000002C PCnext=00000030 ID stage IR=AC02007C rd=00000 EX stage IR=AC010074 EX_A =00000000 EX_B =11111111 EX_C =00000074 rd=00000 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=8C020070 addr =00000070 data =00000000 read =11111111 rd=00010 WB stage IR=08000009 read =00000000 pass =00000009 result=00000009 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 13 inst=8C080074 PC =00000030 PCnext=00000038 ID stage IR=74410002 write=11111111 into =00000002 rd=00000 EX stage IR=AC02007C EX_A =00000000 EX_B =00000000 EX_C =0000007C rd=00000 EX stage EX_aluB=0000007C EX_res=0000007C MEM stage IR=AC010074 addr =00000074 data =11111111 wrote=11111111 rd=00000 WB stage IR=8C020070 read =11111111 pass =00000070 result=11111111 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=1 WB_write_enb=1 reg 0-7 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 44444444 55555555 66666666 00000000 00000000 clock 14 inst=8C050080 PC =00000038 PCnext=0000003C ID stage IR=8C080074 rd=01000 EX stage IR=74410002 EX_A =11111111 EX_B =11111111 EX_C =00000002 rd=00000 EX stage EX_aluB=00000002 EX_res=11111113 MEM stage IR=AC02007C addr =0000007C data =11111111 wrote=11111111 rd=00000 WB stage IR=AC010074 read =11111111 pass =00000074 result=00000074 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=1 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 15 inst=74500003 PC =0000003C PCnext=00000040 ID stage IR=8C050080 rd=00101 EX stage IR=8C080074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=01000 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=74410002 addr =11111113 data =11111111 rd=00000 WB stage IR=AC02007C read =11111111 pass =0000007C result=0000007C rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 16 inst=8C060084 PC =00000040 PCnext=00000044 ID stage IR=74500003 rd=00000 EX stage IR=8C050080 EX_A =00000000 EX_B =00000000 EX_C =00000080 rd=00101 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=8C080074 addr =00000074 data =00000000 read =11111111 rd=01000 WB stage IR=74410002 read =00000000 pass =11111113 result=11111113 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 17 inst=00A6200F PC =00000044 PCnext=00000048 ID stage IR=8C060084 write=11111111 into =00000008 rd=00110 EX stage IR=74500003 EX_A =11111111 EX_B =33333333 EX_C =00000003 rd=00000 EX stage EX_aluB=00000003 EX_res=11111114 MEM stage IR=8C050080 addr =00000080 data =00000000 read =55555555 rd=00101 WB stage IR=8C080074 read =11111111 pass =00000074 result=11111111 rd=01000 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 18 inst=30070070 PC =00000048 PCnext=0000004C ID stage IR=00A6200F write=55555555 into =00000005 rd=00000 EX stage IR=8C060084 EX_A =00000000 EX_B =00000000 EX_C =00000084 rd=00110 EX stage EX_aluB=00000084 EX_res=00000084 MEM stage IR=74500003 addr =11111114 data =33333333 rd=00000 WB stage IR=8C050080 read =55555555 pass =00000080 result=55555555 rd=00101 control RegDst=1 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 11111111 00000000 00000000 55555555 00000000 00000000 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 19 inst=30070070 PC =00000048 PCnext=0000004C ID stage IR=00A6200F rd=00100 EX stage IR=00000000 EX_A =55555555 EX_B =00000000 EX_C =0000200F rd=00000 EX stage EX_aluB=00000000 EX_res=55555555 MEM stage IR=8C060084 addr =00000084 data =00000000 read =66666666 rd=00110 WB stage IR=74500003 read =00000000 pass =11111114 result=11111114 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 00000000 55555555 00000000 00000000 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 20 inst=ACE60000 PC =0000004C PCnext=00000050 ID stage IR=30070070 write=66666666 into =00000006 rd=00111 EX stage IR=00A6200F EX_A =55555555 EX_B =00000000 EX_C =0000200F rd=00100 EX stage EX_aluB=66666666 EX_res=77777777 MEM stage IR=00000000 addr =55555555 data =00000000 rd=00000 WB stage IR=8C060084 read =66666666 pass =00000084 result=66666666 rd=00110 control RegDst=0 ALUSrc=0 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 11111111 00000000 00000000 55555555 66666666 00000000 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 21 inst=AC070080 PC =00000050 PCnext=00000054 ID stage IR=ACE60000 rd=00000 EX stage IR=30070070 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00111 EX stage EX_aluB=00000070 EX_res=00000070 MEM stage IR=00A6200F addr =77777777 data =66666666 rd=00100 WB stage IR=00000000 read =00000000 pass =55555555 result=55555555 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 00000000 55555555 66666666 00000000 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 22 inst=00000000 PC =00000054 PCnext=00000058 ID stage IR=AC070080 write=77777777 into =00000004 rd=00000 EX stage IR=ACE60000 EX_A =00000000 EX_B =66666666 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000070 MEM stage IR=30070070 addr =00000070 data =00000000 rd=00111 WB stage IR=00A6200F read =00000000 pass =77777777 result=77777777 rd=00100 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 11111111 00000000 77777777 55555555 66666666 00000000 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 23 inst=00000000 PC =00000058 PCnext=0000005C ID stage IR=00000000 write=00000070 into =00000007 rd=00000 EX stage IR=AC070080 EX_A =00000000 EX_B =00000000 EX_C =00000080 rd=00000 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=ACE60000 addr =00000070 data =66666666 wrote=66666666 rd=00000 WB stage IR=30070070 read =00000000 pass =00000070 result=00000070 rd=00111 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=1 WB_write_enb=1 reg 0-7 00000000 11111111 11111111 00000000 77777777 55555555 66666666 00000070 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 66666666 11111111 33333333 11111111 55555555 66666666 00000000 00000000 clock 24 inst=00000000 PC =0000005C PCnext=00000060 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=AC070080 addr =00000080 data =00000070 wrote=00000070 rd=00000 WB stage IR=ACE60000 read =66666666 pass =00000070 result=00000070 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=1 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 77777777 55555555 66666666 00000070 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 66666666 11111111 33333333 11111111 00000070 66666666 00000000 00000000 clock 25 inst=00000000 PC =00000060 PCnext=00000064 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=AC070080 read =00000070 pass =00000080 result=00000080 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 77777777 55555555 66666666 00000070 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 66666666 11111111 33333333 11111111 00000070 66666666 00000000 00000000 clock 26 inst=00000000 PC =00000064 PCnext=00000068 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 77777777 55555555 66666666 00000070 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 66666666 11111111 33333333 11111111 00000070 66666666 00000000 00000000 clock 27 inst=00000000 PC =00000068 PCnext=0000006C ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 77777777 55555555 66666666 00000070 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 66666666 11111111 33333333 11111111 00000070 66666666 00000000 00000000 clock 28 inst=00000000 PC =0000006C PCnext=00000070 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 11111111 00000000 77777777 55555555 66666666 00000070 8-15 11111111 00000000 00000000 00000000 00000000 00000000 00000000 22222222 16-23 33333333 66666666 CCCCCCCC 00000000 00000000 00000000 00000000 00000000 RAM 70- 66666666 11111111 33333333 11111111 00000070 66666666 00000000 00000000 Ran until 290 NS + 0 ncsim> exit TOOL: ncsim 15.20-s035: Exiting on Aug 19, 2020 at 21:06:26 EDT (total: 00:00:01)