mips_opcodes.txt from Computer Organization and Design and IRIX.GL slightly different from DLX rd is register destination, the result, general register 1 through 31 rs is the first register source, general register 0 through 31 rt is the second register source, general register 0 through 31 fd is register destination, the result, floating point register fs is the first register source, floating point register ft is the second register source, floating point register --val---- generally a 16 bit number that gets sign extended --adr---- a 16 bit address, gets sign extended abd added to (rx) "i" is generally immediate, operand value is in the instruction "u" is generally unsigned Opcode Operands Machine code format 6 5 5 5 5 6 number of bits in field nop R 00 0 0 0 0 00 break R 00 0 0 0 1 13 add rd,rs,rt R 00 rs rt rd 0 32 addi rd,rs,val I 08 rs rd ---val---- addu rd,rs,rt R 00 rs rt rd 0 33 sub rd,rs,rt R 00 rs rt rd 0 34 subu rd,rs,rt R 00 rs rt rd 0 35 addiu rd,rs,val I 09 rs rd ---val---- mfc0 rd,rt R 16 0 rd rt 0 00 special register mult rs,rt R 00 rs rt 0 0 24 result in Hi, Lo multu rs,rt R 00 rs rt 0 0 25 result in Hi, Lo div rs,rt R 00 rs rt 0 0 26 Lo=quotient, Hi=remainder divu rs,rt R 00 rs rt 0 0 27 Lo=quotient, Hi=remainder mfhi rd R 00 0 0 rd 0 16 Hi -> rd mthi rs R 00 0 0 rs 0 17 rs -> Hi mflo rd R 00 0 0 rd 0 18 Lo -> rd mtlo rs R 00 0 0 rs 0 19 rs -> Lo and rd,rs,rt R 00 rs rt rd 0 36 or rd,rs,rt R 00 rs rt rd 0 37 xor rd,rs,rt R 00 rs rt rd 0 38 nor rd,rs,rt R 00 rs rt rd 0 39 andi rd,rs,val I 12 rs rd ---val---- ori rd,rs,val I 13 rs rd ---val---- xori rd,rs,val I 14 rs rd ---val---- sll rd,rt,shf R 00 0 rt rd shf 00 rt<>shf lw rd,adr(rx) I 35 rx rd ---adr---- sw rt,adr(rx) I 43 rx rt ---adr---- lui rd,val I 15 0 rd ---val---- beq rs,rt,adr I 04 rs rt ---adr---- bne rs,rt,adr I 05 rs rt ---adr---- slt rd,rs,rt R 00 rs rt rd 0 42 slti rd,rs,val I 10 rs rd ---val---- sltu rd,rs,rt R 00 rs rt rd 0 43 sltiu rd,rs,val I 11 rs rd ---val---- j adr J 02 -------adr-------- jr rs R 00 rs 0 0 0 08 jal adr J 03 -------adr-------- jalr rs R 00 rs 0 0 0 09 rfe R 16 16 0 0 0 32 syscall R 00 0 0 0 0 12 Floating Point .s single 32 bit, .d double 64 bit IEEE format c1 is floating point unit, w is general register word add.s fd,fs,ft R 17 16 fs ft fd 00 add.d fd,fs,ft R 17 17 fs ft fd 00 sub.s fd,fs,ft R 17 16 fs ft fd 01 sub.d fd,fs,ft R 17 17 fs ft fd 01 mul.s fd,fs,ft R 17 16 fs ft fd 02 mul.d fd,fs,ft R 17 17 fs ft fd 02 div.s fd,fs,ft R 17 16 fs ft fd 03 div.d fd,fs,ft R 17 17 fs ft fd 03 abs.s fd,fs R 17 16 0 fs fd 05 abs.d fd,fs R 17 17 0 fs fd 05 mov.s fd,fs R 17 16 0 fs fd 06 mov.d fd,fs R 17 17 0 fs fd 06 neg.s fd,fs R 17 16 0 fs fd 07 neg.d fd,fs R 17 17 0 fs fd 07 lwc1 fd,adr(rx) I 49 rx fd ---adr---- swc1 fs,adr(rx) I 57 rx fs ---adr---- ldc1 fd,adr(rx) I 53 rx fd ---adr---- sdc1 fs,adr(rx) I 61 rx fs ---adr---- mfc1 rd,fs R 17 0 fs rd 0 00 mtc1 fd,rs R 17 1 rs fd 0 00 cvt.ws rd,fs R 17 16 0 fs rd 36 cvt.wd rd,fs R 17 17 0 fs rd 36 cvt.sw fd,rs R 17 16 0 rs fd 32 cvt.sd fd,fs R 17 17 0 fs fs 32 cvt.dw rs,fs R 17 16 0 rd fs 33 cvt.ds fd,fs R 17 17 0 fd fs 33