-- hello.vhdl  Just output to the screen
-- compile and run commands
-- 	ncvhdl -v93 hello.vhdl
--	ncelab -v93 hello:circuits
--	ncsim -batch  -logfile hello_vhdl.out -input hello.run hello


entity hello is  -- test bench (top level like "main")
end entity hello;

library STD;
use STD.textio.all;                     -- basic I/O
library IEEE;
use IEEE.std_logic_1164.all;            -- basic logic types
use IEEE.std_logic_textio.all;          -- I/O for logic types

architecture circuits of hello is -- where declarations are placed
  subtype word_32 is std_logic_vector(31 downto 0);
  signal four_32 : word_32 := x"00000004";    -- just four
  signal counter : integer := 1;              -- initialized counter
  alias swrite is write [line, string, side, width] ;
begin  -- where code is placed
  my_print : process is
               variable my_line : line;  -- type 'line' comes from textio
             begin
               write(my_line, string'("Hello VHDL"));  -- formatting
               writeline(output, my_line);              -- write to "output"
               swrite(my_line, "four_32 = ");     -- formatting with alias
               hwrite(my_line, four_32); -- format type std_logic_vector as hex
               swrite(my_line, "  counter= ");
               write(my_line, counter);  -- format 'counter' as integer
               swrite(my_line, " at time ");
               write(my_line, now);                     -- format time
               writeline(output, my_line);              -- write to display
               wait;
             end process my_print;
end architecture circuits;