// hello.v   First Verilog program
// command to compile and run
//         verilog -q -l hello_v.out hello.v

module hello;
  reg [31:0] four_32;
  integer counter;
   
  initial
    begin
      four_32 = 32'b00000000000000000000000000000100; 
      counter = 1;
      $display("Hello Verilog");
      $display("%b", four_32);
      $display("counter = %d", counter); 
    end
endmodule // hello