Data forwarding example   CMSC 411 architecture

  Consider the five stage pipeline architecture:

  IF instruction fetch, PC is address into memory fetching instruction
  ID instruction decode and register read out of two values
  EX execute instruction or compute data memory address
  M  data memory access to store or fetch a data word
  WB write back value into general register


         IF       ID       EX        M       WB
    +--+     +--+     +--+     +--+     +--+
    |  |     |  |     |  |-|\  |  |     |  |
    |  |     |  |    /|  | \ \_|  |     |  |
    |PC|-(I)-|IR|-(R) |  | / / |  |-(D)-|  |--+
    |  |     |  |  ^ \|  |-|/  |  |     |  |  |
    +--+     +--+  |  +--+     +--+     +--+  |
     ^        ^    |   ^   ALU  ^        ^    |
     |        |    |   |        |        |    |
 clk-+--------+--------+--------+--------+    |
                   |                          |
                   +--------------------------+

  Now consider the instruction sequence:

  400  lw  $1,100($0)  load general register 1 from memory location 100
  404  lw  $2,104($0)  load general register 2 from memory location 104
  408  add $3,$1,$2    add contents of registers 1 and 2, sum into register 3
  40C  add $4,$3,$1    add contents of registers 3 and 1, sum into register 4
  410  beq $3,$4,-100  branch, if contents of register 3 and 4 are equal,
                       to location 310
  414  add $4,$4,$4    add ..., this is the "delayed branch slot" always exec.

  The pipeline stage table with NO data forwarding is:

  lw   IF ID EX M  WB
  lw      IF ID EX M  WB
  add        IF ID -  -  EX M  WB
  add           IF -  -  ID -  -  EX M  WB
  beq                    IF -  -  ID -  - *EX M  WB    * beq becomes nop
  add                             IF -  -  ID EX M  WB

  time 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16
  a dash represents a stall of the pipeline

  The pipeline stage table with data forwarding is:

  lw   IF ID EX M  WB
  lw      IF ID EX M  WB
  add        IF ID -  EX M  WB        (hazard, must stall)
  add           IF -  ID EX M  WB
  beq                 IF ID - *EX M  WB     * beq becomes a nop
  add                    IF -  ID EX M  WB 

  time 1  2  3  4  5  6  7  8  9  10 11 12
  a dash represents a stall of the pipeline

  Note the inherent stall from using data immediately after a load.
  The hazard unit must know what the data forwarding unit can do.
  

  The data forwarding rules can be summarized based on the
  cs411 schematics.

  ID stage beq data forwarding: 

      default with no data forwarding is ID_read_data_1      
      1 forward MEM_addr is  ID_reg1=MEM_RD and MEM_rd/=0 and MEM_OP/=lw 
  
      default with no data forwarding is ID_read_data_2
      2 forward MEM_addr is  ID_reg2=MEM_RD and MEM_rd/=0 and MEM_OP/=lw 

  EX stage data forwarding:

      default with no data forwarding is EX_A
      A forward MEM_addr is  EX_reg1=MEM_RD and MEM_RD/=0 and MEM_OP/=lw
      A forward WB_result is  EX_reg1=WB_RD and WB_RD/=0

      default with no data forwarding is EX_B
      B forward MEM_addr is  EX_reg2=MEM_RD and MEM_RD/=0 and MEM_OP/=lw
      B forward WB_result is  EX_reg2=WB_RD and WB_RD/=0

      Note: the entity mux32_3 is designed to handle the above.

  ID_RD is 0 for ID_OP= beq, j, sw (nop automatic zero)
           thus EX_RD, MEM_RD,  WB_RD = 0 for these instructions


  note: ID_reg1 is ID_IR(25 downto 21)
        ID_reg2 is ID_IR(20 downto 16)
        EX_reg1 is EX_IR(25 downto 21)
        EX_reg2 is EX_IR(20 downto 16)
        MEM_OP  is MEM_IR(31 downto 26)

        These shorter names can be used with  VHDL alias statements

        alias  ID_reg1 : word_5 is ID_IR(25 downto 21);
        alias  ID_reg2 : word_5 is ID_IR(20 downto 16);
        alias  EX_reg1 : word_5 is EX_IR(25 downto 21);
        alias  EX_reg2 : word_5 is EX_IR(20 downto 16);
        alias  MEM_OP  : word_6 is MEM_IR(31 downto 26);