// fadd.v  Verilog 1 bit adder made from and-or  and  nand gates
// run  verilog -q -l fadd.out fadd.v
`timescale 1ns/1ns

module fadda(a, b, cin, sum, cout); // and-or from truth table
  input  a;     // a input
  input  b;     // b input
  input  cin;   // carry-in
  output sum;   // sum output
  output cout;  // carry-out
  assign sum = (~a&~b&cin)|(~a&b&~cin)|(a&~b&~cin)|(a&b&cin);
  assign cout = (a&b)|(a&cin)|(b&cin); // last term redundant
endmodule // fadda

module faddn(a, b, cin, sum, cout); // using only universal nand
  input  a;     // a input
  input  b;     // b input
  input  cin;   // carry-in
  output sum;   // sum output
  output cout;  // carry-out
  assign sum = (~(~a&~b&cin))&(~(~a&b&~cin))&(~(a&~b&~cin))&(~(a&b&cin));
  assign cout = (~(a&b))&(~(a&cin))&(~(b&cin)); // last term redundant
endmodule // faddn

module fadd;  // test bench
  // signals used in test bench (the interconnections)
  
  reg  a;
  reg  b; 
  reg  c;
  wire s;
  wire co;
  reg  an;
  reg  bn; 
  reg  cn;
  wire sn;
  wire con;
  integer i, j, k;
  reg val[1:4];

  // instantiate modules with signal names
  fadda andor(a, b, c, s, co); 
  faddn nand1(an, bn, cn, sn, con);
    
  initial
    begin
      val[1] = 0;
      val[2] = 1;
      val[3] = 1'b x;
      val[4] = 1'b z;

      #5 $display("\na b c | s=a+b+c bit   co carry bit  and-or");
      for(i=1; i<=2; i=i+1)
      begin
        a = val[i];
        for(j=1; j<=2; j=j+1)
        begin
          b = val[j];
          for(k=1; k<=2; k=k+1)
          begin
            c = val[k];
            // circuit 
            // fadda(a, b, c, s, co); // andor
            #5 $display("%b %b %b | %b %b ", a, b, c, s, co);
	  end
        end
      end

      #5 $display("\na b c | s=a+b+c bit   co carry bit  nand");
      for(i=1; i<=2; i=i+1)
      begin
        a = val[i];
        for(j=1; j<=2; j=j+1)
        begin
          b = val[j];
          for(k=1; k<=2; k=k+1)
          begin
            c = val[k];
            // circuit 
            // faddn(a, b, c, s, co); // nand1
            #5 $display("%b %b %b | %b %b ", a, b, c, s, co);
	  end
        end
      end

    end
endmodule // fadd