// div4.v  Verilog 8 bits divided by 4 bits made with  cas modules
// run  verilog -q -l div4_v.out div4.v
`timescale 1ns/1ns
  
module cas(T, rem, div, cin, rout, cout); // from schematic
  input  T;     // T input, quotient bit or 1
  input  rem;   // remainder_in input
  input  div;   // divisor input
  input  cin;   // carry_in
  output rout;  // remainder_out
  output cout;  // carry_out
  assign rout = (T^div)^rem^cin;
  assign cout = ((T^div)&rem)|((T^div)&cin)|(rem&cin);
endmodule // cas

module mul4;  // test bench
  // signals used in test bench (the interconnections)
  
  reg   [6:0] dnd; // dividend
  reg   [3:0] div; // divisor
  reg 	one; 
  wire  [36:0] rout;   // intermediate routs 
  wire  [36:0] cout;   // intermediate couts 
  wire  [3:0] quo;     // quotient
  wire [3:0] rem;      // remainder
   
  // instantiate modules with signals
  //         T        rem       div     cin      rout      cout

  cas bit33(one,     dnd[3],   div[0], one,      rout[33], cout[33]);
  cas bit34(one,     dnd[4],   div[1], cout[33], rout[34], cout[34]);
  cas bit35(one,     dnd[5],   div[2], cout[34], rout[35], cout[35]);
  cas bit36(one,     dnd[6],   div[3], cout[35], rout[36], cout[36]);
  assign quo[3] = ~rout[36];

  cas bit22(quo[3],  dnd[2],   div[0], quo[3],   rout[22], cout[22]);
  cas bit23(quo[3],  rout[33], div[1], cout[22], rout[23], cout[23]);
  cas bit24(quo[3],  rout[34], div[2], cout[23], rout[24], cout[24]);
  cas bit25(quo[3],  rout[35], div[3], cout[24], rout[25], cout[25]);
  assign quo[2] = ~rout[25];

  cas bit11(quo[2],  dnd[1],   div[0], quo[2],   rout[11],  cout[11]);
  cas bit12(quo[2],  rout[22], div[1], cout[11], rout[12],  cout[12]);
  cas bit13(quo[2],  rout[23], div[2], cout[12], rout[13],  cout[13]);
  cas bit14(quo[2],  rout[24], div[3], cout[13], rout[14],  cout[14]);
  assign quo[1] = ~rout[14];

  cas bit00(quo[1],  dnd[0],   div[0], quo[1],   rem[0],    cout[0]);
  cas bit01(quo[1],  rout[11], div[1], cout[0],  rem[1],    cout[1]);
  cas bit02(quo[1],  rout[12], div[2], cout[1],  rem[2],    cout[2]);
  cas bit03(quo[1],  rout[13], div[3], cout[2],  rem[3],    cout[3]);
  assign quo[0] = ~rem[3];

  always
    begin
      $display("div4.v running");
      one = 1;
      dnd = 7'b1111011;
      div   = 4'b1100; 
       
      #15 $display("dnd=%b, div=%b, quo=%b, rem=%b", dnd, div, quo, rem);
      $display(" ");
      $display("cout=%b", cout);
      $display("rout=%b", rout);
      $display(" ");
       
      dnd = 7'b1010101;
      div   = 4'b0111; 

      #15 $display("dnd=%b, div=%b, quo=%b, rem=%b", dnd, div, quo, rem);
      $display(" ");
       
      dnd = 7'b0000000;
      div   = 4'b0001; 

      #15 $display("dnd=%b, div=%b, quo=%b, rem=%b", dnd, div, quo, rem);
      $display(" ");
       
      $finish;
    end
endmodule // div4