// dff.v  verilog D flip flops

module dff6(d, c, s, r, q, q_);
  input  d;     // q follows d when c goes 0 to 1
  input  c;     // clock, state change on transition
  input  s;     // set q to 1 when s is zero, keep s high
  input  r;     // set q to 0 when r is zero, keep r high
  output q;     // normal output
  output q_;    // complement output
  reg d1, d1_, d2, d2_, q, q_;

  always @(d, c, s, r)
    begin
      d1  = ~(d1_ & s & d2_);
      d1_ = ~(d1  & c & r  );
      d2  = ~(d2_ & c & d1_);
      d2_ = ~(d2  & r & d  );
      q   = ~(q_  & s & d1_);
      q_  = ~(q   & r & d2 );
    end
endmodule // dff6

module dff4(d, c, q, q_);
  input  d;     // q follows d when c is 1
  input  c;     // clock, state change on level
  output q;     // normal output
  output q_;    // complement output
  wire d1, d2, d_;

  not     (d_, d);
  nand #1 (d1, d,  c );
  nand #1 (d2, d_, c );
  nand #1 (q,  q_, d1);
  nand #1 (q_, q,  d2);
endmodule // dff4