Example on debugging using  diff  and project output

(first part of project output)
ncsim: 06.11-s008: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncsim> run 280 ns
---PC--- --inst--  loadmem process input .abs file
00000000 8C010070 	lw   $1,w1($0)
00000004 8C020074 	lw   $2,w2($0)
00000008 8C030078 	lw   $3,w3($0)
0000000C 00000000 	nop
00000010 00000000 	nop
00000014 00232020 	add  $4,$1,$3
00000018 00222822 	sub  $5,$1,$2
0000001C 000133C2 	sll  $6,$1,15
00000020 00023C03 	srl  $7,$2,16  <---  see register 7, thus srl  ***
00000024 0003400B 	cmpl $8,$3      
00000028 0022480D 	or   $9,$1,$2
0000002C 0023500A 	and  $10,$1,$3
00000030 0062581B 	mul  $11,$3,$2
00000034 00436018 	div  $12,$2,$3

(from .chk file after seeing diff output below)
clock 10  inst=0022480D  PC   =00000028 PCnext=0000002C
ID  stage  IR=0003400B  write=EEEEEEEF  into =00000005                 rd=01000
EX  stage  IR=00023C03  EX_A =00000000  EX_B =22222222  EX_C =00003C03 rd=00111
EX  stage             EX_aluB=22222222 EX_res=00002222 <--- shifted ***
MEM stage  IR=000133C2  addr =88888000  data =11111111                 rd=00110
WB  stage  IR=00222822  read =00000000  pass =EEEEEEEF result=EEEEEEEF rd=00101
control RegDst=1  ALUSrc=0  MemtoReg=0  MEMRead=0  MEMWrite=0  WB_write_enb=1
reg 0-7 00000000 11111111 22222222 33333333 44444444 EEEEEEEF 00000000 00000000 
   8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 
  16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 
RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000
(From diff)
160c160
< EX  stage             EX_aluB=22222222 EX_res=22222222
---
> EX  stage             EX_aluB=22222222 EX_res=00002222  <--- *** difference
173c173
< MEM stage  IR=00023C03  addr =22222222  data =22222222                 rd=00111
---
> MEM stage  IR=00023C03  addr =00002222  data =22222222                 rd=00111
182c182
< ID  stage  IR=0023500A  write=22222222  into =00000007                 rd=01010
---
> ID  stage  IR=0023500A  write=00002222  into =00000007                 rd=01010
186c186
< WB  stage  IR=00023C03  read =00000000  pass =22222222 result=22222222 rd=00111
---
> WB  stage  IR=00023C03  read =00000000  pass =00002222 result=00002222 rd=00111
188c188
< reg 0-7 00000000 11111111 22222222 33333333 44444444 EEEEEEEF 88888000 22222222 
---
> reg 0-7 00000000 11111111 22222222 33333333 44444444 EEEEEEEF 88888000 00002222 
                                                                         *****
(Register 7, find instruction that sets this register)
((fix srlop ))