// add4.v  Verilog 4 bit adder made from  fadd modules
// run  verilog -q -l add4.out add4.v
`timescale 1ns/1ns
  
module fadd(a, b, cin, sum, cout); // from truth table
  input  a;     // a input
  input  b;     // b input
  input  cin;   // carry-in
  output sum;   // sum output
  output cout;  // carry-out
  assign sum = (~a&~b&cin)|(~a&b&~cin)|(a&~b&~cin)|(a&b&cin);
  assign cout = (a&b)|(a&cin)|(b&cin); // last term redundant
endmodule // fadd

module add4;  // test bench
  // signals used in test bench (the interconnections)
  
  reg  [3:0] a;
  reg  [3:0] b; 
  reg  cin;
  wire  [3:0] sum;
  wire  [3:0] c;  // intermediate couts 
  wire  cout;

  // instantiate modules
  fadd bit0(a[0], b[0], cin,  sum[0], c[0]);
  fadd bit1(a[1], b[1], c[0], sum[1], c[1]);
  fadd bit2(a[2], b[2], c[1], sum[2], c[2]);
  fadd bit3(a[3], b[3], c[2], sum[3], cout);
  
  always
    begin
      $display("add4.v running");
      a   = 4'b1011;
      b   = 4'b1000; 
      cin = 1;
      #5 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b",
                   a, b, cin, sum, cout);

      a   = 4'b0000;
      b   = 4'b0000; 
      cin = 0;
      #5 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b",
                   a, b, cin, sum, cout);

      a   = 4'b1111;
      b   = 4'b1111; 
      cin = 1;
      #5 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b",
                   a, b, cin, sum, cout);

      $finish;
    end
endmodule // add4